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Papers
This page describes some of the general technical papers and presentations produced by the authors on this site. Please contact the author if what you are looking for is missing from this list.
| Title | Date | Place | Description |
|---|---|---|---|
| Test ER: Triage Millions of Tests [Slides] | 2007-10 | Design Verification Club Boston | Our future work on writing BugVise to automatically triage test run failures. By Wilson Snyder. See also BugVise. |
| Ten IP Edits [Paper], Ten IP Edits [Slides] | 2007-09 | Synopsys User's Group Boston | RTL Edits commonly made to integrate IP. By Wilson Snyder. |
| SiCortex Functional Verification [Paper], SiCortex Functional Verification [Slides] | 2007-06 | DAC | Techniques and tools used to verify the SiCortex System on a Chip. By Oleg Petlin. |
| Verilator Internals [Slides] | 2005-07 | Philips Semiconductors | The history, usage, and some internals of Verilator. By Wilson Snyder. See also Verilator. |
| Verilator SystemC Environment [Slides] | 2004-06 | North American SystemC User's Group/ DAC | Using Verilator inside a SystemC environment. By Wilson Snyder. See also Verilator. |
| 505 Registers or Bust [Paper], 505 Registers or Bust [Slides] | 2001-08 | Synopsys User's Group Boston | Using Vregs to capture register declarations from specifications. By Wilson Snyder. See also Vregs. |
| Veritedium [Paper], Veritedium [Slides] | 2001-03 (Updated 2006-01) | San Jose Synopsys User's Group | Using Verilog-mode to simplify Verilog coding. By Wilson Snyder. See also Verilog-Mode. |
| Synthesisizable Watchdog Logic [Paper], Synthesisizable Watchdog Logic [Slides] | 2000 | Synopsys User's Group Boston | Using Vpm to insert assertions. By Duane Galbi. Won the Best Technical Paper award. See also Verilog-Perl. |
| Boa Methodology [Paper], Boa Methodology [Slides] | 1997-02 | Synopsys User's Group (San Jose and Europe) | Early synthesis methodology allowing easy signal time budgeting. |