Index by title

Verilog-Perl Documentation ¶

Primary documentation is available as man pages after installation.

Presentations¶

Vpm was presented by &DGALBI; at the 2000 Boston Synopsys User's Group meeting. The paper, titled Synthesizable Watchdog Logic: A Key Coding Strategy for Managing Complex Designs won the Best Technical Paper award.

VPM Technical Paper

VPM Presentation Slides

Verilog-Perl Mailing Lists ¶

If you wish to receive email announcements of releases (same as the news items seen here), send an email to:

verilog-perl-announce-subscribe

And append the typical at-sign veripool.org to that email address. (Aren't email harvesters a pain!)

There may be a developer mailing list in the near future; we are debating the usefulness of it relative to using the bug tracker and forums on this site. Let the forums know your opinions on this.

For archives of verilog-perl-announce, see the News tab above.

Installing Verilog-Perl ¶

Installation with CPAN¶

If you're using a recent version of Perl, just:

cpan install Verilog::Language
# And read the documentation
man Verilog-Perl

Download¶

Alternatively, download from CPAN/wsnyder. Then

tar xvzf Verilog-Perl*.t*gz
cd Verilog-Perl-*

perl Makefile.PL
make
make test
make install

And see the kit's README.

Repository¶

Alternatively, you can get the entire development repository with:

git clone http://git.veripool.org/git/Verilog-Perl
cd Verilog-Perl
git tag         # See what versions exist (recent GITs only)
# Skip next line if wish to use HEAD development version
#git checkout Verilog-Perl_{version}  # Switch to specified version

perl Makefile.PL
make
make test
make install

Prerequisites¶

Verilog-Perl should run on any operating system with Perl and a C++ complier. Note some older Linux distributions have versions of Perl that do not support C++ modules and might not install automatically with CPAN.

Introduction to Verilog-Perl ¶

Written by Wilson Snyder <wsnyder@wsnyder.org>.

Summary¶

The Verilog-Perl library is a building point for Verilog support in the Perl language. It includes:

Verilog::Getopt which parses command line options similar to C++ and VCS.

Verilog::Language which knows the language keywords and parses numbers.

Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules.

Verilog::Parser invokes callbacks for language tokens.

Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files.

vpm preprocesses warnings and assertions for any simulator.

vppp preprocesses the complete Verilog 2001 and SystemVerilog language.

vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes.

Verilog-Perl Documentation¶