Index by title

Verilog-mode Change History

Verilog-mode Documentation

Program Documentation

Verilog-Mode help pages (from Emacs)

Verilog-Mode FAQ (Frequently Asked Questions)

Verilog-Mode Change History

Papers and Presentations

Verilog-mode was presented by Wilson Snyder <wsnyder@wsnyder.org> at the 2001 San Jose Synopsys User's Group meeting. The paper is titled Verilog-Mode: Reducing the Veri-Tedium.

Veritedium Technical Paper (.html)

Veritedium Presentation Slides (.pdf)

Verilog-Mode Examples

Text examples

See the Faq for many examples of expanding Verilog AUTOs, and the presentations under the Documentation.

Screenshots

We start with a simple Verilog module in Emacs:

   

And just by installing Verilog-Mode we get syntax highlighting and automatic indentation. Hit two keys and AUTO keywords expand.

   

Verilog-mode Faq

This is the Frequently Asked Questions (FAQ) for Verilog-mode. This FAQ is Copyright 2006-2008 by Michael McNamara and Wilson Snyder. You may redistribute this document in its entirety only, and the links to www.Verilog.com and www.Veripool.org must be retained.

Table of Contents

Obtaining, and general information

Where is the most up to date version of this FAQ?

The official released version of this document is the Verilog-Mode FAQ, from http://www.veripool.org/wiki/verilog-mode/Faq.

Where do I get Verilog-Mode?

The official released version of Verilog-Mode is distributed by Michael McNamara from his <A HREF="http://www.verilog.com">Verilog site</A>. You can also subscribe to get mailed updates.

Versions are also available from the Veripool under Verilog-mode.

How do I install Verilog-Mode?

See Installation.

Are there other Verilog Modes for Emacs?

The authors are only aware of one which have been maintained within the last half-dozen years.

Sun Yijiang maintains vlog-mode.el from http://sourceforge.net/projects/vlog-mode. His version supports GNU Emacs and he has started adding some Verilog 2001 support.

Competition is good; if you prefer vlog-mode.el, we'd like to hear back as to if there are features we could also add to in verilog-mode.el.

Can I release Verilog-Mode with my tool?

Yes. Verilog-Mode is released under the GNU General Public License. See the license for the full legal details, but fundamentally distributing it stand-alone with a commercial tool is no problem, you merely need to insure verilog-mode.el remains available to everyone. If you didn't make any changes, you're all set, else you'll need to post your version on a public website, or better, feed the changes back to the authors for inclusion in the base version.

Entering Verilog-Mode

Using viper, why when I load a verilog file does it loose viper?

You need to tell viper that it is ok with you for files in verilog to come up in verilog-mode and viper.

To do that, type 
M-x customize RET viper-misc

Then scroll down and find the item Vi State Mode List Left-Click on the triangle to open this up.

Scroll down through the blizzard of listed modes to the bottom. You should see: 
[INS] [DEL] Symbol: csh-mode
[INS] [DEL] Symbol: gnus-article-mode
[INS] [DEL] Symbol: mh-show-mode
[INS]
   [State]: this option has been set and saved.
Major modes that require Vi command state

Middle-click on the bare INS; you should get:

[INS] [DEL] Symbol: mh-show-mode
[INS] [DEL] Symbol: nil
[INS]
   [State]

Then left-click on nil, and replace the string 'nil' with verilog-mode You should get:

[INS] [DEL] Symbol: mh-show-mode
[INS] [DEL] Symbol: verilog-mode
[INS]
   [State]

Now middle-click on [State] and a pop up menu appears; select Set for Current Session and then also middle click again and select Save for Future Sessions.

Now if you are running viper, when you load a verilog file, it will start in viper mode.

Why do I get the message "File mode specification error:"?

Or, the similar messages:

File mode specification error:  (void-function define-skeleton)
File mode specification error: (file-error "Cannot open load file" "overlay")

You need skeleton.el, part of the base package for the first, or overlay.el, part of the fsf-compatibility package for the second, which are both XEmacs lisp packages, which you somehow have not installed, or have not updated.

Go to Tools -> Packages ->Add download site and pick a site (xemacs.org works for me)

Then select Tools -> Packages -> List and Install

Go to the bottom, and click on the line that says xemacs-base. to get the skeleton.el file. You will see something like:

                 Latest Installed
  Package name   Vers.  Vers.   Description
============================================================
  Sun             1.13   1.13   Support for Sparcworks.
     ...
  w3              1.18   1.18   A Web browser.
* xemacs-base     1.53   1.51   Fundamental XEmacs support.
- xemacs-devel    1.33   -----  Emacs Lisp developer support.
- xslt-process    1.03   -----  XSLT processing support.
  zenirc          1.09   1.09   ZENIRC IRC Client.
============================================================

For the overlay package, click on the line that says <font color="red">fsf-compat</font>. to get the overlay.el file. In this case you will see something like:

                 Latest Installed
  Package name   Vers.  Vers.   Description
============================================================
  Sun             1.13   1.13   Support for Sparcworks.
     ...

  w3              1.18   1.18   A Web browser.
* fsf-compat      1.12   ----   FSF EMacs compatibility files
  zenirc          1.09   1.09   ZENIRC IRC Client.
============================================================

When you click on it, the * changes to a +

Then type x, which will install the package.

Then restart XEmacs and things should then work just fine.

Indentation

How do I indent a large region of code?

Typing TAB on every line can get old...

Use C-M-\ to indent a region (selected by setting the point at one end, and having the cursor at the other end, as usual). Perhaps a future version of the emacs mode will include functions that mimic some of C's extra bindings.

How do I reindent Verilog code from the command line?

You can repair the indentation of a Verilog file from the command line with the following command:

emacs --batch {filenames...} -f verilog-batch-indent

This will load the file, reindent, and save the file.

If your verilog-mode.el is not installed in a site-wide location, or you suspect you are getting the wrong version, try specifing the exact path to Verilog-Mode by adding -l {path}/verilog-mode.el after --batch.

Additional information is in Emacs under M-x describe-function verilog-batch-indent.

Why when others edit my code does it looks unindented?

This is a general problem sharing files between folks. It also occurs between folks using the same editor, as many editors allow one to set the tab width. The general solution is for you to add a write file hook that expands tabs to spaces.

Add the following to your .emacs file: (or init.el file for XEmacs 21 users.)

(add-hook 'verilog-mode-hook '(lambda ()
    (add-hook 'local-write-file-hooks (lambda()
       (untabify (point-min) (point-max))))))

This arranges so that any file in verilog mode (the "add-hook 'verilog-mode-hook" part) gets added to it's 'local-write-file-hooks' a call to the function 'untabify' with arguments that are the first and last character in the buffer. Untabify converts all tabs in the region to multiple spaces.

Why can't I insert tabs in some places in the file?

This is because tab is a electric key that causes reindentation. See another FAQ for how to disable this.

If you want to manually space something out, in general, in Emacs you can escape the special meaning of any key by first typing C-q, which quotes the next key.

How do I prevent tab from automatically indenting?

Set the verilog-tab-always-indent variable to nil. If your goal is minimal intrusion of magic keys, you'll probably also want to set verilog-auto-newline to nil.

Add to your .emacs file:

(add-hook 'verilog-mode-hook
      '(lambda ()
         (setq verilog-auto-newline nil)
         (setq verilog-tab-always-indent nil)
      )))

How do I prevent those // comments at the end of blocks?

Set verilog-auto-endcomments to nil:

(setq verilog-auto-endcomments nil)

Why does Verilog-Mode hang reading a huge file?

To debug the problem, type

M-x eval-expression RET
(setq debug-on-quit t)

Then load the file. After 10 seconds or whatever hit Ctrl-G to stop Emacs. It will show in the debugger what it's doing.

If you're using a older flavor of Emacs, most of the time it will stop somewhere in "fontification". Simply disable fontification (coloring) of larger files. Put into your .emacs:

(setq font-lock-maximum-size 100000)

Why do I not get any colors in huge files?

This is sort of the opposite of the last FAQ; any file exceeding the default size of 256,000 characters will not get font-locked. To override this, put into your .emacs:

(setq font-lock-maximum-size 2000000)

Alternatively, load the lazy-lock package. This will only highlight the region on the screen. To find it, use 

M-x find-library RET
lazy-lock
.

Language Support

Why does the signal "bit", "do", "const" get ignored?

They're keywords. Unfortunately the SystemVerilog committee made these into new keywords, but did not provide a way to make Verilog 1995 code forward compatible by leaving them as signal names until the Verilog 2005 standard, which we don't fully support yet. You need to rename your signals.

Can I use Verilog-Mode to do 'generate' like code?

There's no general way to do this with Verilog-Mode. Obviously you can use AUTOINST to simplify the code, then ifdef, but that isn't very clean.

When I've needed to do a true generate, I often read signals with Verilog-Perl, then write the text with printf's or the Perl Text::Template module. I then pass the output of this through Emacs Verilog-Mode --batch, and walla.

Movement

How can I jump the cursor to the file that defines a module?

Use \M-x verilog-goto-defun (C-c\C-d).

How can I invoke my compiler?

Use M-x compile, or M-x verilog-auto-save-compile (C-c C-s). This looks at the verilog-tool setting and chooses your linter, coverage, simulator or compiler. The verilog-linter is the default.

So, in your .emacs set reasonable defaults for all of them:

(setq verilog-tool 'verilog-linter)
(setq verilog-linter "vlint ...")
(setq verilog-coverage "coverage ...)
(setq verilog-simulator "verilator ... ")
(setq verilog-compiler "verilator ... "

Then, if a file needs a special setting, override it at the bottom of each Verilog file:

// Local Variables:
// verilog-linter:"vlint --local_options __FILE__" 
// End:

How do I go to the next error?

After using M-x compile, or M-x verilog-auto-save-compile (C-c C-s), you'll get the compile buffer. If errors are printed there, you can jump to the line number the message mentions with M-x next-error (C-x `). Or, place the cursor over the error message and press return.

If this does not work with your tool, the tool probably does not produce errors in a standard way. You'll need to tweak the verilog-error-regexp variable. This contains a regular expression which matches a error message and returns the file and line number.

Autos

How do I start using the autos for the first time?

There are two easy ways to get started. The first is to convert an existing file, and the second is covered in the next FAQ.

To convert an existing file to use the autos, use M-x verilog-auto-inject (C-c C-z). Then, expand them with M-x verilog-auto (C-c C-s).

What AUTOs should I use for a new file?

Here's a good template for a first file:

module Modname (/*AUTOARG*/);

   // Input/output
   //input signal;    // Comment on signal

   // Automatics
   /*AUTOWIRE*/
   /*AUTOREG*/

   // Body
   //statements, etc go here.

   // Linting
   wire _unused_ok = &amp;{1'b0,
               // Put list of unused signals here
               1'b0};
endmodule

You'd then add cells using AUTOINST:

   InstModule instName
     (/*AUTOINST*/);

(The newline before the open parenthesis is suggested for larger instantiations to make the lines look nicer.)

And add sensitivity blocks using AUTOSENSE (aka AS):

   always @(/*AS*/) begin   // or, @* if using Verilog-2001
      ...
   end

How do I make a Stub module?

A stub is a module with the same input/output as another module, but it simply ignores all the inputs and drives zeros for outputs. This is often useful for replacing modules that aren't needed for a simulation.

By using several Autos, the entire stub can be created for you:

module ModnameStub (/*AUTOARG*/);
   /*AUTOINOUTMODULE("Modname")*/

   /*AUTOWIRE*/
   /*AUTOREG*/

   /*AUTOTIEOFF*/

   wire _unused_ok = &amp;{1'b0,
               /*AUTOUNUSED*/
               1'b0};
endmodule

This presumes Modname.v already exists and you want to copy the entire I/O list from it. Otherwise, remove the AUTOINOUTMODULE and add the I/O list yourself.

How do I make a Testbench module?

A testbench for the purposes of this question is a module which instantiates another module for the purpose of testing it.

By using several Autos, most of the hookup for the testbench are created for you:

module ModnameTest;

   /*AUTOWIRE*/
   /*AUTOREGINPUT*/

   InstModule instName
     (/*AUTOINST*/);

   //==== Stimulus
   // You then put code here to set all of the inputs to the DUT.
   // The autos have created registers for all of the needed signals.

   //==== Stimulus
   // You then put code here to check all of the outputs from the DUT.
   // The autos have created wires for all of the needed signals.

endmodule

How do I update AUTOs from the command line?

Use the following command:

emacs --batch {filenames...} -f verilog-batch-auto

This will load the file, update the automatics, and re-save the file. The filenames need to be provided in a bottom-up order. For a utility to determine the hierarchy of a design, see vhier in Verilog-Perl.

If your verilog-mode.el is not installed in a site-wide location, or you suspect you are getting the wrong version, try specifing the exact path to Verilog-Mode by adding -l {path}/verilog-mode.el after --batch.

There are similar functions for deleting automatics using verilog-batch-delete-auto, injecting automatics with verilog-batch-inject-auto, and reindenting with verilog-batch-indent.

Additional information is in Emacs under M-x describe-function verilog-batch-auto, etc.

How do I tell the AUTOs what directories my files are in?

The cleanest way is to use standard Verilog-XL style flags at the bottom of your Verilog file:

// Local Variables:
// verilog-library-flags:("-y incdir1/ -y incdir2/")
// End:

You'll also often see files that do it in the way that old Verilog-Mode versions required:

// Local Variables:
// verilog-library-directories:("." "dir1" "dir2" ...)
// End:

If you find yourself adding the same flags to many files, you can create a file with all of your include directories in it, then point Emacs to it. All of your Verilog files would contain:

// Local Variables:
// verilog-library-directories:("-f ../../up_to_top/include/input.vc")
// End:

Then input.vc contains the list of flags:

-y incdir1
-y incdir2
...

Note reading a file of command flags with the -f argument is also supported by Verilog-XL, VCS, Verilator and most other Verilog related tools. Thus you can write a single input.vc with all of the directories specified and feed it to all of your tools.

How do I use environment variables for a filename, etc?

Emacs only expands $'s when you ask it to do so by using substitute-in-file-name. So, if you want to substitute $ENV into a Local Variables in the bottom of your file, you need something like:

// Local Variables:
// eval:(setq verilog-library-directories (list (substitute-in-file-name "$W") ))
// End:

In what order does Verilog-Mode search for modules?

It first searches the current file, then searches for the module.v in each directory you provided in the order you provided. If the module isn't found, it searches any libraries specified.

Generally it's a really really bad idea to have files with the same name in different directories... But you probably know that. :)

How do I make defaults common for my entire design team?

First, you may not want to. If you're distributing IP you're much better off using the Local Variables at the bottom of the file, and insuring all of your file paths are relative. That way your clients can modify the AUTOs without any tweaks.

That said, add the following to site-start.el in your global Emacs distribution:

(add-hook 'verilog-mode-hook '(lambda ()
                (setq verilog-auto-newline nil
                      verilog-tab-always-indent nil
                      verilog-auto-endcomments nil
                      verilog-compiler "verilator " 
                      ;; etc, etc...
                      )))

Alternatively, add the above to a group-start.el file and have all users add a group-startup to their .emacs files:

(when (file-exists-p "/path/to/group/group-start.el")
          (load-file "/path/to/group/group-start.el"))

AUTO problems

How do I use Verilog 2001 style port lists?

Place AUTOINPUT/AUTOOUTPUT etc inside the module () parenthesis.

Does anything help declare non-instance wires and regs?

No. AUTOWIRE and AUTOREG all assume that somewhere in your design you've declared the signal. This is based on the belief that there should be at least one point where you've declared the signal, and hopefully documented it on the same line.

Why does Emacs keep asking "Process `eval' or hook local variables in file?"

You need to put in your global .emacs

(setq enable-local-eval t)

Why doesn't Emacs save SystemVerilog .* expanded instantiations to disk?

When you compute autos, Verilog-Mode will find any SystemVerilog .* pins and expand them into the ports, so that you can debug your code more easily. By default it will then strip these inserted lines when saving the file. This allows downstream tools to see the original SystemVerilog syntax, and not require re-autoing when the submodules change.

If you want to save the expanded .* pins, add to the Local Variables at the bottom of your file.

// Local Variables:
// verilog-auto-star-save: t
// End:

Why does AUTOSENSE add `defines to the list?

Call it a misfeature. :-)

Take the case where you have

always @(/*AS*/)
   ...
   a = `b;

and b isn't defined. Is b a constant, or another signal? No way to tell, it's safest to put it in the always. Granted, b could simply be defined in the file. If so, you can tell Verilog-Mode to read defines in the current file, and any `includes using:

// Local Variables:
// eval:(verilog-read-defines)
// eval:(verilog-read-includes)
// End:

If you only use defines to represent constants, it's easier to just tell Verilog-Mode that fact, and it will exclude all of them:

// Local Variables:
// verilog-auto-sense-defines-constant: t
// End:

Why do the AUTOs treat SystemVerilog types as signals?

You need to tell Verilog-Mode how to recognize a type. All of your types should match some convention, a _t suffix is probably the most common. Then add to your files:

// Local Variables:
// verilog-typedef-regexp:"_t$" 
// End:

Why do the AUTOS ignore my ifdefs?

Verilog-Mode simply pretends all ifdefs don't exist. This is done because the permutations across multiple ifdefs quickly results in code that's way too messy. The work around is all the AUTOs ignore declarations that already exist, or are done before the AUTO itself.

For example:

   module foo (
`ifdef something
    things,
`endif
    /*AUTOARG*/);

   subfile subcell (
`ifdef something
    things,
`endif
    /*AUTOINST*/);

If your selecting modules, see the next FAQ.

If your ifdefing around signals for only debug, there's rarely a need to do so. Synthesis programs will remove irrelevant logic and ignore PLI calls.

An alternative technique to have a fake "mode" input wire, rather than a ifdef or parameter. This also prevents having to lint or run other translators in 2 different `define modes, thus reducing bugs. This also relies on your synthesis program's removal of irrelevant stuff. For example a unneeded input and output can always be present, and instead:

    input          FPGA;
    input         fpga_only_input;
    output [31:0] fpga_only_output;

    if (fpga_only_input &amp;&amp; FPGA) ...
    fpga_only_output = {32{FPGA}} &amp; {value_for_output}.

Both will be stripped when FPGA=0, and present when FPGA=1.

How do I ifdef select between modules?

Often the purpose of an ifdef is to select between two alternate implementations of a module with identical pinouts; perhaps a fast RAM and a slow gate RAM. Your first attempt may be something similar to:

`ifdef SUB_IS_A_FOOBAR
   foobar subcell (/*AUTOINST*/);
`else
   foobiz subcell (/*AUTOINST*/);
`endif

However, Verilog-mode ignores ifdefs. Assuming the pinout is the same you can use the define to instead select which version:

`ifdef SUB_IS_A_FOOBAR
 `define SUB_CELL  foobar
`else
 `define SUB_CELL  foobiz
`endif
   `SUB_CELL subcell (/*AUTOINST*/);

for this to work, you need to read the defines with the below at the bottom of your file. Verilog-mode will use the last definition of SUB_CELL to determine which one to pickup the pinlist from.

// Local Variables:
// eval:(verilog-read-defines)
// End:

Can I put delays into /*AUTORESET*/?

That is,

/*AUTORESET*/
foo <= #1 signal;

Do you really want to? You really shouldn't be using delays on your assignments, as they aren't necessary to prevent races, and slows down simulation. But if you must:

// Local Variables:
// verilog-assignment-delay: "#1 " 
// End:

Can AUTOASCIIENUM be changed to put translate_off pragmas around the code?

No. First of all, you'd be better of asking to wrap it "`ifdef synthesis" as that lets the tools pick which version of the code you want.

Second, there isn't one standard way that supports all tools.

Third, presuming you never use the value it generates at all (or only in $display's) there's no reason to disable translation, as the synthesis tool will rip it all out through its normal dead code optimization stage.

How do I remove outputs from AUTOOUTPUT?

Maybe you shouldn't be using AUTOOUTPUT? Consider listing your outputs manually; this insures your module's interface is documented and remains constant, even if other lower modules change.

With that warning given, on to the solutions. You have four choices, the last probably being the most used:

First, just ifdef fake outputs. Verilog-mode will see them, but no other tool will care. This is cleanest for signals you can list one-by-one, and are using Verilog 2001 port lists or when you want those listed to still appear in a AUTOARG.

`ifdef NEVER
        output a_out;   // Fake out Verilog-mode
        output b_out;   // Fake out Verilog-mode
`endif

Second alternative, simply create a fake module listing them as inputs. Since Verilog-Mode will then see them as inputs to a submodule, it won't output them.

`ifdef NEVER
  fake fake (// Inputs
        .fake(a_out),
        .fake(b_out),
        );
`endif

Third alternative, you can add them to verilog-auto-output-ignore-regexp using Local Variables:

/*
   Local Variables:
   eval:(setq verilog-auto-output-ignore-regexp (concat
   "^\\(" 
   "signal1_.*" 
   "\\|signal2_.*" 
   "\\)$" 
   )))
   End:
*/

Finally, you can again use verilog-auto-output-ignore-regexp, but use a AUTO_LISP. This gets around a Emacs limitation of 3000 characters in a Local Variable statement.

 /*AUTO_LISP(setq verilog-auto-output-ignore-regexp
             (verilog-regexp-words `(
        "q_single_reg_rddata_30" 
        )))*/

Here we've used verilog-regexp-words to convert a simple list of signal names to a regular expression. If you prefer, you can just specify a regular expression directly, perhaps as shown in the Local Variables alternative above.

Note AUTO_LISPs are evaluated during AUTO expansion multiple times instead of only when the file is loaded into Emacs. Thus it's a bit slower, but unlikely to be noticeable.

Why doesn't AUTOWIRE include the outputs from a submodule?

AUTOWIRE requires special comments in your instantiations to determine the direction of pins. Add // Input, // Output or // Inout comments inside each instantiation just before the relevant pins.

   foo foo ( // Outputs
        .bfm_output(bfm_output),
        ....)

Why doesn't AUTOWIRE create correct widths for AUTO_TEMPLATE signals?

You simply need to add [] to the name of the pin connection. This tells Verilog-Mode to put the bit vectors into the instantiation, where they can be read by AUTOWIRE.

/* InstModule AUTO_TEMPLATE ( .signal (signal[]), ); */

What does AUTOWIRE "can't merge into single bus" mean?

When there are multiple submodules that output the same signal, AUTOWIRE needs to merge those outputs into a single bus. For example, if one instantiation outputs a[1:0], and the second instantiation outputs a[3:2], then AUTOWIRE needs to declare wire a[3:0].

This error message means that it cannot determine how to declare that vector. Usually this is because you used parameters or something complicated in the instantiations. You'll need to declare that wire yourself.

How do I use AUTO_TEMPLATE to tie off inputs to zero?

Use a LISP format template, and the lisp variable vl-width, which contains the width of the port.

/* InstModule AUTO_TEMPLATE (
    .\(.*\)_test ({@"vl-width"{1'b0}}),
);
*/

How do I use AUTO_TEMPLATE to lower case all signals?

Use a lisp expression, and the lisp function "downcase".

/* InstModule AUTO_TEMPLATE (
   .IN (@"(downcase vl-name)"[]),
*/

If you're trying the reverse, namely to upcase your signal names, did you consider lower case is more readable by 15% or so than all upper case?

How do I use AUTO_TEMPLATE to include the instantiation name for pin?

Yet another lisp expression:

/* InstModule AUTO_TEMPLATE (
     .a(@"vl-cell-name"_in[]),
     .b(@"vl-cell-name"_out[]),
     );*/

InstModule u_a0 (/*AUTOINST*/
     // Inouts
     .a    (u_a0_in[bitsa:0]),     // Templated
     .b    (u_a0_out[bitsb:0]));     // Templated
InstModule u_a1 (/*AUTOINST*/
     // Inouts
     .a    (u_a1_in[bitsa:0]),     // Templated
     .b    (u_a1_out[bitsb:0]));     // Templated

Oh, but what if I didn't want the u_?

/* InstModule AUTO_TEMPLATE (
     .a(@"(substring vl-cell-name 2)"_in[]),
     .b(@"(substring vl-cell-name 2)"_out[])
     );*/

InstModule u_a0 (/*AUTOINST*/
   // Inouts
   .a    (a0_in[bitsa:0]),     // Templated
   .b    (a0_out[bitsb:0]));     // Templated

Substring is very useful in templates. All of your cell names need to be the same length however. Often you can simply pad the names by adding zeros, for example use u_00 ... u_15, rather than u_0 ... u_15.

How do I have AUTO_TEMPLATE use the second number in a instance name?

The standard @ sign in a template by default returns the first number in a instance name, so if you want a earlier number, you have three main choices.

If you only need the second digit, you can define the @ sign to come from the second digits in the module:

/* InstModule AUTO_TEMPLATE ".*[0-9]+.*\([0-9]\)" (
                             .a (in_@),
*/

Next easiest is to use @"(substring vl-cell-name ...) to extract the relevant digits. See the examples above.

The most flexible is to define your own function to do the relevant extraction, then call it. For example:

/* AUTO_LISP(defun getparam2 (strg)
    (string-match "[^0-9]*[0-9]+[^0-9]*\\([0-9]+\\)" strg)
    (match-string 1 strg)) */

/* InstModule AUTO_TEMPLATE (
    .in (@"(getparam2 vl-cell-name)"),
    );
    */

How do I use AUTO_TEMPLATE to connect bytes to instances?

This is for when you want the first instance to get a[7:0], the second a[15:8], and so on.

Use a lisp template and a little math.

/* InstModule AUTO_TEMPLATE (
     .a(@in[@"(+ (* 8 @) 7)":@"(* 8 @)"]),
     );*/

InstModule u_a0 (/*AUTOINST*/
     .a    (in[7:0]));     // Templated
InstModule u_a1 (/*AUTOINST*/
     .a    (in[15:8]));     // Templated
InstModule u_a2 (/*AUTOINST*/
     .a    (in[23:16]));     // Templated
InstModule u_a3 (/*AUTOINST*/
     .a    (in[31:24]));     // Templated

How do I use AUTOINST with Synplify syn_prune attributes?

Synplify documentation suggests placing attributes just before the final semicolon of instance names. Instead place the comment before the list of ports, which works just as well, and has the additional advantage of being close to the instantiated module name (instead of potentially pages lower if there's many pins.) Synplify has been notified of this issue, and is likely to change their documentation.

InstModule u_a0 /*synthesis syn_noprune=1*/
  (/*AUTOINST*/
     .a    (a));

Installing Verilog-Mode

Download

Michael McNamara <mac@verilog.com> distributes the latest version from his website, www.verilog.com. Registering there will enable you to receive announcements as new versions are released.

The most recent version is also found here:

verilog-mode.el.gz (89KB, Nov 21 2008)
verilog-mode.el (383KB, Nov 21 2008)

Or, the last few versions:

verilog-mode-463.el.gz (89KB, Nov 21 2008)
verilog-mode-460.el.gz (89KB, Nov 11 2008)
verilog-mode-458.el.gz (89KB, Nov 08 2008)
verilog-mode-457.el.gz (89KB, Oct 30 2008)
verilog-mode-446.el.gz (88KB, Oct 07 2008)

To see what's changed, see Verilog-Mode Change History

Important Download Tip

Note some browsers will truncate these files if you click on the link to open it. Instead:

If using Firefox, right-click on verilog-mode.el and "Save Target As" verilog-mode.el.

If using Explorer, right-click on verilog-mode.el and "Save Link As." Choose to save the file, then when the save dialog shows up, change the filename from the wrongly defaulted "verilog-mode.el.htm" to "verilog-mode.el". (Currently only some versions of Explorer 7 botch the filename; Thanks Microsoft.)

Install

Place verilog-mode.el in your Emacs load-path, and add a few lines to your site-start .emacs file. See the instructions at the top of the program for details.

Prerequisites

Verilog-mode.el runs on any operating system with a recent GNU Emacs or XEmacs.

Introduction to Verilog-Mode

Written by Michael McNamara <mac@verilog.com> and Wilson Snyder <wsnyder@wsnyder.org>.

Summary

Verilog-mode.el is a free Verilog mode for Emacs which provides context-sensitive highlighting, auto indenting, and provides macro expansion capabilities to greatly reduce Verilog coding time.

Recent versions allow you to insert AUTOS in non-AUTO designs, so IP interconnect can be easily modified. You can also expand Verilog-2001 ".*" instantiations, to see what ports will be connected by simulators.

Popularity

Verilog-mode.el is being used by thousands of engineers world wide. The Verilog AUTOS are in use by many of the leading IP providers, including IP processor cores sold by MIPS and ARM.

See also

See the buttons at the top of this page, which include:

Verilog-Mode installation and download

Verilog-Mode examples and screen shots

Verilog-Mode FAQ

Verilog-Mode documentation, papers and presentations

Other Sites

Verilog.com is Michael McNamara (one of the author's) site. Here you can register to get mail about Verilog-Mode.

Note to Searchers

If you're looking for Verylog-mode or an Emacs mode for Verylog HDL, this is it, you just need to correct your spelling. :)

This page contains documentation extracted from verilog-mode, revision 463. Functions are described here beginning with verilog-mode and verilog-auto, then alphabetically.

See also the other Verilog-mode Documentation

You may copy this document, but it will soon get out of date; you are thus better linking to &BASE;verilog-mode-help.html, or getting these pages from the Emacs help system.

Copyright 2006, the Free Software Foundation. By Michael McNamara (mac@verilog.com). and Wilson Snyder (wsnyder@wsnyder.org)

verilog-mode (function)

Major mode for editing Verilog code.

See M-x describe-function verilog-auto (M-x verilog-auto) for details on how AUTOs can improve coding efficiency.

Use M-x verilog-faq for a pointer to frequently asked questions.

NEWLINE, TAB indents for Verilog code. Delete converts tabs to spaces as it moves back.

Supports highlighting.

Turning on Verilog mode calls the value of the variable verilog-mode-hook with no args, if that value is non-nil.

Variables controlling indentation/edit style:

variable verilog-indent-level (default 3)

Indentation of Verilog statements with respect to containing block.
verilog-indent-level-module (default 3)
Absolute indentation of Module level Verilog statements. Set to 0 to get initial and always statements lined up on the left side of your screen.
verilog-indent-level-declaration (default 3)
Indentation of declarations with respect to containing block. Set to 0 to get them list right under containing block.
verilog-indent-level-behavioral (default 3)
Indentation of first begin in a task or function block Set to 0 to get such code to lined up underneath the task or function keyword.
verilog-indent-level-directive (default 1)
Indentation of `ifdef/`endif blocks.
verilog-cexp-indent (default 1)
Indentation of Verilog statements broken across lines i.e.: 
      if (a)
        begin
verilog-case-indent (default 2)
Indentation for case statements.
verilog-auto-newline (default nil)
Non-nil means automatically newline after semicolons and the punctuation mark after an end.
verilog-auto-indent-on-newline (default t)
Non-nil means automatically indent line after newline.
verilog-tab-always-indent (default t)
Non-nil means TAB in Verilog mode should always reindent the current line, regardless of where in the line point is when the TAB command is used.
verilog-indent-begin-after-if (default t)
Non-nil means to indent begin statements following a preceding if, else, while, for and repeat statements, if any. Otherwise, the begin is lined up with the preceding token. If t, you get: 
      if (a)
         begin // amount of indent based on verilog-cexp-indent
otherwise you get: 
      if (a)
      begin
verilog-auto-endcomments (default t)
Non-nil means a comment /* ... */ is set after the ends which ends cases, tasks, functions and modules. The type and name of the object will be set between the braces.
verilog-minimum-comment-distance (default 10)
Minimum distance (in lines) between begin and end required before a comment will be inserted. Setting this variable to zero results in every end acquiring a comment; the default avoids too many redundant comments in tight quarters.
verilog-auto-lineup (default `(all))
List of contexts where auto lineup of code should be done.

Variables controlling other actions:

verilog-linter (default surelint)

Unix program to call to run the lint checker. This is the default command for M-x compile-command and M-x verilog-auto-save-compile.

See M-x customize for the complete list of variables.

AUTO expansion functions are, in part: 

    M-x verilog-auto  Expand AUTO statements.
    M-x verilog-delete-auto  Remove the AUTOs.
    M-x verilog-inject-auto  Insert AUTOs for the first time.

Some other functions are: 

    M-x verilog-complete-word    Complete word with appropriate possibilities.
    M-x verilog-mark-defun  Mark function.
    M-x verilog-beg-of-defun  Move to beginning of current function.
    M-x verilog-end-of-defun  Move to end of current function.
    M-x verilog-label-be  Label matching begin ... end, fork ... join, etc statements.


    M-x verilog-comment-region  Put marked area in a comment.
    M-x verilog-uncomment-region  Uncomment an area commented with M-x verilog-comment-region.
    M-x verilog-insert-block  Insert begin ... end.
    M-x verilog-star-comment    Insert /* ... */.


    M-x verilog-sk-always  Insert an always @(AS) begin .. end block.
    M-x verilog-sk-begin  Insert a begin .. end block.
    M-x verilog-sk-case  Insert a case block, prompting for details.
    M-x verilog-sk-for  Insert a for (...) begin .. end block, prompting for details.
    M-x verilog-sk-generate  Insert a generate .. endgenerate block.
    M-x verilog-sk-header  Insert a header block at the top of file.
    M-x verilog-sk-initial  Insert an initial begin .. end block.
    M-x verilog-sk-fork  Insert a fork begin .. end .. join block.
    M-x verilog-sk-module  Insert a module .. (/*AUTOARG*/);.. endmodule block.
    M-x verilog-sk-primitive  Insert a primitive .. (.. );.. endprimitive block.
    M-x verilog-sk-repeat  Insert a repeat (..) begin .. end block.
    M-x verilog-sk-specify  Insert a specify .. endspecify block.
    M-x verilog-sk-task  Insert a task .. begin .. end endtask block.
    M-x verilog-sk-while  Insert a while (...) begin .. end block, prompting for details.
    M-x verilog-sk-casex  Insert a casex (...) item: begin.. end endcase block, prompting for details.
    M-x verilog-sk-casez  Insert a casez (...) item: begin.. end endcase block, prompting for details.
    M-x verilog-sk-if  Insert an if (..) begin .. end block.
    M-x verilog-sk-else-if  Insert an else if (..) begin .. end block.
    M-x verilog-sk-comment  Insert a comment block.
    M-x verilog-sk-assign  Insert an assign .. = ..; statement.
    M-x verilog-sk-function  Insert a function .. begin .. end endfunction block.
    M-x verilog-sk-input  Insert an input declaration, prompting for details.
    M-x verilog-sk-output  Insert an output declaration, prompting for details.
    M-x verilog-sk-state-machine  Insert a state machine definition, prompting for details.
    M-x verilog-sk-inout  Insert an inout declaration, prompting for details.
    M-x verilog-sk-wire  Insert a wire declaration, prompting for details.
    M-x verilog-sk-reg  Insert a register declaration, prompting for details.
    M-x verilog-sk-define-signal  Define signal under point as a register at the top of the module.

All key bindings can be seen in a Verilog-buffer with M-x describe-bindings. Key bindings specific to verilog-mode-map are:

\{verilog-mode-map}

verilog-auto (function)

Expand AUTO statements. Look for any /*AUTO...*/ commands in the code, as used in instantiations or argument headers. Update the list of signals following the /*AUTO...*/ command.

Use M-x verilog-delete-auto to remove the AUTOs.

Use M-x verilog-inject-auto to insert AUTOs for the first time.

Use M-x verilog-faq for a pointer to frequently asked questions.

The hooks verilog-before-auto-hook and verilog-auto-hook are called before and after this function, respectively.

For example: 

	module ModuleName (/*AUTOARG*/)
	/*AUTOINPUT*/
	/*AUTOOUTPUT*/
	/*AUTOWIRE*/
	/*AUTOREG*/
	InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);

You can also update the AUTOs from the shell using: 

	emacs --batch  <filenames.v>  -f verilog-batch-auto
Or fix indentation with: 
	emacs --batch  <filenames.v>  -f verilog-batch-indent
Likewise, you can delete or inject AUTOs with: 
	emacs --batch  <filenames.v>  -f verilog-batch-delete-auto
	emacs --batch  <filenames.v>  -f verilog-batch-inject-auto

Using M-x describe-function, see also: 

    verilog-auto-arg          for AUTOARG module instantiations
    verilog-auto-ascii-enum   for AUTOASCIIENUM enumeration decoding
    verilog-auto-inout-comp  for AUTOINOUTCOMP copy complemented i/o
    verilog-auto-inout-module for AUTOINOUTMODULE copying i/o from elsewhere
    verilog-auto-inout        for AUTOINOUT making hierarchy inouts
    verilog-auto-input        for AUTOINPUT making hierarchy inputs
    verilog-auto-inst         for AUTOINST instantiation pins
    verilog-auto-star         for AUTOINST .* SystemVerilog pins
    verilog-auto-inst-param   for AUTOINSTPARAM instantiation params
    verilog-auto-output       for AUTOOUTPUT making hierarchy outputs
    verilog-auto-output-every for AUTOOUTPUTEVERY making all outputs
    verilog-auto-reg          for AUTOREG registers
    verilog-auto-reg-input    for AUTOREGINPUT instantiation registers
    verilog-auto-reset        for AUTORESET flop resets
    verilog-auto-sense        for AUTOSENSE always sensitivity lists
    verilog-auto-tieoff       for AUTOTIEOFF output tieoffs
    verilog-auto-unused       for AUTOUNUSED unused inputs/inouts
    verilog-auto-wire         for AUTOWIRE instantiation wires


    verilog-read-defines      for reading `define values
    verilog-read-includes     for reading `includes

If you have bugs with these autos, try contacting the AUTOAUTHOR Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.org.

verilog-active-low-regexp (customizable variable)

If set, treat signals matching this regexp as active low. This is used for AUTORESET and AUTOTIEOFF. For proper behavior, you will probably also need verilog-auto-reset-widths set.

verilog-auto-arg (function)

Expand AUTOARG statements. Replace the argument declarations at the beginning of the module with ones automatically derived from input and output statements. This can be dangerous if the module is instantiated using position-based connections, so use only name-based when instantiating the resulting module. Long lines are split based on the `fill-column', see M-x set-fill-column.

Limitations:

Concatenation and outputting partial busses is not supported.

Typedefs must match verilog-typedef-regexp, which is disabled by default.

For example: 

	module ExampArg (/*AUTOARG*/);
	  input i;
	  output o;
	endmodule

Typing M-x verilog-auto will make this into: 

	module ExampArg (/*AUTOARG*/
	  // Outputs
	  o,
	  // Inputs
	  i
	);
	  input i;
	  output o;
	endmodule

Any ports declared between the ( and /*AUTOARG*/ are presumed to be predeclared and are not redeclared by AUTOARG. AUTOARG will make a conservative guess on adding a comma for the first signal, if you have any ifdefs or complicated expressions before the AUTOARG you will need to choose the comma yourself.

Avoid declaring ports manually, as it makes code harder to maintain.

verilog-auto-ascii-enum (function)

Expand AUTOASCIIENUM statements, as part of M-x verilog-auto. Create a register to contain the ASCII decode of a enumerated signal type. This will allow trace viewers to show the ASCII name of states.

First, parameters are built into a enumeration using the synopsys enum comment. The comment must be between the keyword and the symbol. (Annoying, but that's what Synopsys's dc_shell FSM reader requires.)

Next, registers which that enum applies to are also tagged with the same enum. Synopsys also suggests labeling state vectors, but verilog-mode doesn't care.

Finally, a AUTOASCIIENUM command is used.

The first parameter is the name of the signal to be decoded.

The second parameter is the name to store the ASCII code into. For the signal foo, I suggest the name _foo__ascii, where the leading _ indicates a signal that is just for simulation, and the magic characters _ascii tell viewers like Dinotrace to display in ASCII format.

The final optional parameter is a string which will be removed from the state names.

An example: 

	//== State enumeration
	parameter [2:0] // synopsys enum state_info
			   SM_IDLE =  3'b000,
			   SM_SEND =  3'b001,
			   SM_WAIT1 = 3'b010;
	//== State variables
	reg [2:0]	/* synopsys enum state_info */
			state_r;		/* synopsys state_vector state_r */
	reg [2:0]	/* synopsys enum state_info */
			state_e1;


	//== ASCII state decoding


	/*AUTOASCIIENUM("state_r", "state_ascii_r", "SM_")*/

Typing M-x verilog-auto will make this into: 

	... same front matter ...


	/*AUTOASCIIENUM("state_r", "state_ascii_r", "SM_")*/
	// Beginning of automatic ASCII enum decoding
	reg [39:0]		state_ascii_r;		// Decode of state_r
	always @(state_r) begin
	   case ({state_r})
		SM_IDLE:  state_ascii_r = "idle ";
		SM_SEND:  state_ascii_r = "send ";
		SM_WAIT1: state_ascii_r = "wait1";
		default:  state_ascii_r = "%Erro";
	   endcase
	end
	// End of automatics

verilog-auto-endcomments (customizable variable)

True means insert a comment /* ... */ after 'end's. The name of the function or case will be set between the braces.

verilog-auto-hook (customizable variable)

Hook run after verilog-mode updates AUTOs.

verilog-auto-indent-on-newline (customizable variable)

True means automatically indent line after newline.

verilog-auto-inout (function)

Expand AUTOINOUT statements, as part of M-x verilog-auto. Make inout statements for any inout signal in an /*AUTOINST*/ that isn't declared elsewhere inside the module.

Limitations:

This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls).

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

If any concatenation, or bit-subscripts are missing in the AUTOINSTant's instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).

Typedefs must match verilog-typedef-regexp, which is disabled by default.

Signals matching verilog-auto-inout-ignore-regexp are not included.

An example (see verilog-auto-inst for what else is going on here): 

	module ExampInout (ov,i)
	   input i;
	   /*AUTOINOUT*/
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into: 

	module ExampInout (ov,i)
	   input i;
	   /*AUTOINOUT*/
	   // Beginning of automatic inouts (from unused autoinst inouts)
	   inout [31:0]	ov;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
	     (/*AUTOINST*/
	      // Inouts
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting inouts starting with i: 

	   /*AUTOINOUT("^i")*/

verilog-auto-inout-comp (function)

Expand AUTOINOUTCOMP statements, as part of M-x verilog-auto. Take input/output/inout statements from the specified module and insert the inverse into the current module (inputs become outputs and vice-versa.) This is useful for making test and stimulus modules which need to have complementing I/O with another module. Any I/O which are already defined in this module will not be redefined.

Limitations:

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

Concatenation and outputting partial busses is not supported.

Module names must be resolvable to filenames. See verilog-auto-inst.

Signals are not inserted in the same order as in the original module, though they will appear to be in the same order to a AUTOINST instantiating either module.

An example: 

	module ExampShell (/*AUTOARG*/)
	   /*AUTOINOUTCOMP("ExampMain")*/
	endmodule


	module ExampMain (i,o,io)
          input i;
          output o;
          inout io;
        endmodule

Typing M-x verilog-auto will make this into: 

	module ExampShell (/*AUTOARG*/i,o,io)
	   /*AUTOINOUTCOMP("ExampMain")*/
           // Beginning of automatic in/out/inouts (from specific module)
           output i;
           inout io;
           input o;
	   // End of automatics
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting signals starting with i: 

	   /*AUTOINOUTCOMP("ExampMain","^i")*/

verilog-auto-inout-ignore-regexp (customizable variable)

If set, when creating AUTOINOUT list, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.

verilog-auto-inout-module (function)

Expand AUTOINOUTMODULE statements, as part of M-x verilog-auto. Take input/output/inout statements from the specified module and insert into the current module. This is useful for making null templates and shell modules which need to have identical I/O with another module. Any I/O which are already defined in this module will not be redefined.

Limitations:

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

Concatenation and outputting partial busses is not supported.

Module names must be resolvable to filenames. See verilog-auto-inst.

Signals are not inserted in the same order as in the original module, though they will appear to be in the same order to a AUTOINST instantiating either module.

An example: 

	module ExampShell (/*AUTOARG*/)
	   /*AUTOINOUTMODULE("ExampMain")*/
	endmodule


	module ExampMain (i,o,io)
          input i;
          output o;
          inout io;
        endmodule

Typing M-x verilog-auto will make this into: 

	module ExampShell (/*AUTOARG*/i,o,io)
	   /*AUTOINOUTMODULE("ExampMain")*/
           // Beginning of automatic in/out/inouts (from specific module)
           output o;
           inout io;
           input i;
	   // End of automatics
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting signals starting with i: 

	   /*AUTOINOUTMODULE("ExampMain","^i")*/

verilog-auto-input (function)

Expand AUTOINPUT statements, as part of M-x verilog-auto. Make input statements for any input signal into an /*AUTOINST*/ that isn't declared elsewhere inside the module. This is useful for modules which only instantiate other modules.

Limitations:

This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls).

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

If any concatenation, or bit-subscripts are missing in the AUTOINSTant's instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).

Typedefs must match verilog-typedef-regexp, which is disabled by default.

Signals matching verilog-auto-input-ignore-regexp are not included.

An example (see verilog-auto-inst for what else is going on here): 

	module ExampInput (ov,i)
	   output [31:0] ov;
	   /*AUTOINPUT*/
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into: 

	module ExampInput (ov,i)
	   output [31:0] ov;
	   /*AUTOINPUT*/
	   // Beginning of automatic inputs (from unused autoinst inputs)
	   input	i;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
	     (/*AUTOINST*/
	      // Outputs
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting inputs starting with i: 

	   /*AUTOINPUT("^i")*/

verilog-auto-input-ignore-regexp (customizable variable)

If set, when creating AUTOINPUT list, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.

verilog-auto-inst (function)

Expand AUTOINST statements, as part of M-x verilog-auto. Replace the pin connections to an instantiation with ones automatically derived from the module header of the instantiated netlist.

If verilog-auto-star-expand is set, also expand SystemVerilog .* ports, and delete them before saving unless verilog-auto-star-save is set. See verilog-auto-star for more information.

Limitations:

Module names must be resolvable to filenames by adding a verilog-library-extensions, and being found in the same directory, or by changing the variable verilog-library-flags or verilog-library-directories. Macros `modname are translated through the vh-{name} Emacs variable, if that is not found, it just ignores the `.

In templates you must have one signal per line, ending in a ), or ));, and have proper () nesting, including a final ); to end the template.

Typedefs must match verilog-typedef-regexp, which is disabled by default.

SystemVerilog multidimensional input/output has only experimental support.

Parameters referenced by the instantiation will remain symbolic, unless verilog-auto-inst-param-value is set.

For example, first take the submodule InstModule.v: 

	module InstModule (o,i)
	   output [31:0] o;
	   input i;
	   wire [31:0] o = {32{i}};
	endmodule

This is then used in a upper level module: 

	module ExampInst (o,i)
	   output o;
	   input i;
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into: 

	module ExampInst (o,i)
	   output o;
	   input i;
	   InstModule instName
	     (/*AUTOINST*/
	      // Outputs
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

Where the list of inputs and outputs came from the inst module.

Exceptions:

Unless you are instantiating a module multiple times, or the module is something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY. It just makes for unmaintainable code. To sanitize signal names, try vrename from http://www.veripool.org.

When you need to violate this suggestion there are two ways to list exceptions, placing them before the AUTOINST, or using templates.

Any ports defined before the /*AUTOINST*/ are not included in the list of automatics. This is similar to making a template as described below, but is restricted to simple connections just like you normally make. Also note that any signals before the AUTOINST will only be picked up by AUTOWIRE if you have the appropriate // Input or // Output comment, and exactly the same line formatting as AUTOINST itself uses. 

	InstModule instName
          (// Inputs
	   .i		(my_i_dont_mess_with_it),
	   /*AUTOINST*/
	   // Outputs
	   .ov		(ov[31:0]));

Templates:

For multiple instantiations based upon a single template, create a commented out template: 

	/* InstModule AUTO_TEMPLATE (
		.sig3	(sigz[]),
		);
	*/

Templates go ABOVE the instantiation(s). When an instantiation is expanded verilog-mode simply searches up for the closest template. Thus you can have multiple templates for the same module, just alternate between the template for an instantiation and the instantiation itself.

The module name must be the same as the name of the module in the instantiation name, and the code "AUTO_TEMPLATE" must be in these exact words and capitalized. Only signals that must be different for each instantiation need to be listed.

Inside a template, a [] in a connection name (with nothing else inside the brackets) will be replaced by the same bus subscript as it is being connected to, or the [] will be removed if it is a single bit signal. Generally it is a good idea to do this for all connections in a template, as then they will work for any width signal, and with AUTOWIRE. See PTL_BUS becoming PTL_BUSNEW below.

If you have a complicated template, set verilog-auto-inst-template-numbers to see which regexps are matching. Don't leave that mode set after debugging is completed though, it will result in lots of extra differences and merge conflicts.

For example: 

	/* InstModule AUTO_TEMPLATE (
		.ptl_bus	(ptl_busnew[]),
		);
	*/
	InstModule ms2m (/*AUTOINST*/);

Typing M-x verilog-auto will make this into: 

	InstModule ms2m (/*AUTOINST*/
	    // Outputs
	    .NotInTemplate	(NotInTemplate),
	    .ptl_bus		(ptl_busnew[3:0]),  // Templated
	    ....

@ Templates:

It is common to instantiate a cell multiple times, so templates make it trivial to substitute part of the cell name into the connection name.
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