Verilog-mode

This page contains documentation extracted from verilog-mode, revision 463. Functions are described here beginning with verilog-mode and verilog-auto, then alphabetically.

See also the other Verilog-mode Documentation

You may copy this document, but it will soon get out of date; you are thus better linking to &BASE;verilog-mode-help.html, or getting these pages from the Emacs help system.

Copyright 2006, the Free Software Foundation. By Michael McNamara (mac@verilog.com). and Wilson Snyder (wsnyder@wsnyder.org)

Use M-x verilog-faq for a pointer to frequently asked questions.

NEWLINE, TAB indents for Verilog code. Delete converts tabs to spaces as it moves back.

Supports highlighting.

Turning on Verilog mode calls the value of the variable verilog-mode-hook with no args, if that value is non-nil.

Variables controlling indentation/edit style:

variable verilog-indent-level (default 3)

Indentation of Verilog statements with respect to containing block.

Absolute indentation of Module level Verilog statements. Set to 0 to get initial and always statements lined up on the left side of your screen.

Indentation of declarations with respect to containing block. Set to 0 to get them list right under containing block.

Indentation of first begin in a task or function block Set to 0 to get such code to lined up underneath the task or function keyword.

Indentation of `ifdef/`endif blocks.

Indentation of Verilog statements broken across lines i.e.:

      if (a)
        begin

Indentation for case statements.

Non-nil means automatically newline after semicolons and the punctuation mark after an end.

Non-nil means automatically indent line after newline.

Non-nil means TAB in Verilog mode should always reindent the current line, regardless of where in the line point is when the TAB command is used.

Non-nil means to indent begin statements following a preceding if, else, while, for and repeat statements, if any. Otherwise, the begin is lined up with the preceding token. If t, you get:

      if (a)
         begin // amount of indent based on verilog-cexp-indent

otherwise you get:

      if (a)
      begin

Non-nil means a comment /* ... */ is set after the ends which ends cases, tasks, functions and modules. The type and name of the object will be set between the braces.

Minimum distance (in lines) between begin and end required before a comment will be inserted. Setting this variable to zero results in every end acquiring a comment; the default avoids too many redundant comments in tight quarters.

List of contexts where auto lineup of code should be done.

Variables controlling other actions:

verilog-linter (default surelint)

Unix program to call to run the lint checker. This is the default command for M-x compile-command and M-x verilog-auto-save-compile.

See M-x customize for the complete list of variables.

AUTO expansion functions are, in part:

    M-x verilog-auto  Expand AUTO statements.
    M-x verilog-delete-auto  Remove the AUTOs.
    M-x verilog-inject-auto  Insert AUTOs for the first time.

Some other functions are:

    M-x verilog-complete-word    Complete word with appropriate possibilities.
    M-x verilog-mark-defun  Mark function.
    M-x verilog-beg-of-defun  Move to beginning of current function.
    M-x verilog-end-of-defun  Move to end of current function.
    M-x verilog-label-be  Label matching begin ... end, fork ... join, etc statements.

    M-x verilog-comment-region  Put marked area in a comment.
    M-x verilog-uncomment-region  Uncomment an area commented with M-x verilog-comment-region.
    M-x verilog-insert-block  Insert begin ... end.
    M-x verilog-star-comment    Insert /* ... */.

    M-x verilog-sk-always  Insert an always @(AS) begin .. end block.
    M-x verilog-sk-begin  Insert a begin .. end block.
    M-x verilog-sk-case  Insert a case block, prompting for details.
    M-x verilog-sk-for  Insert a for (...) begin .. end block, prompting for details.
    M-x verilog-sk-generate  Insert a generate .. endgenerate block.
    M-x verilog-sk-header  Insert a header block at the top of file.
    M-x verilog-sk-initial  Insert an initial begin .. end block.
    M-x verilog-sk-fork  Insert a fork begin .. end .. join block.
    M-x verilog-sk-module  Insert a module .. (/*AUTOARG*/);.. endmodule block.
    M-x verilog-sk-primitive  Insert a primitive .. (.. );.. endprimitive block.
    M-x verilog-sk-repeat  Insert a repeat (..) begin .. end block.
    M-x verilog-sk-specify  Insert a specify .. endspecify block.
    M-x verilog-sk-task  Insert a task .. begin .. end endtask block.
    M-x verilog-sk-while  Insert a while (...) begin .. end block, prompting for details.
    M-x verilog-sk-casex  Insert a casex (...) item: begin.. end endcase block, prompting for details.
    M-x verilog-sk-casez  Insert a casez (...) item: begin.. end endcase block, prompting for details.
    M-x verilog-sk-if  Insert an if (..) begin .. end block.
    M-x verilog-sk-else-if  Insert an else if (..) begin .. end block.
    M-x verilog-sk-comment  Insert a comment block.
    M-x verilog-sk-assign  Insert an assign .. = ..; statement.
    M-x verilog-sk-function  Insert a function .. begin .. end endfunction block.
    M-x verilog-sk-input  Insert an input declaration, prompting for details.
    M-x verilog-sk-output  Insert an output declaration, prompting for details.
    M-x verilog-sk-state-machine  Insert a state machine definition, prompting for details.
    M-x verilog-sk-inout  Insert an inout declaration, prompting for details.
    M-x verilog-sk-wire  Insert a wire declaration, prompting for details.
    M-x verilog-sk-reg  Insert a register declaration, prompting for details.
    M-x verilog-sk-define-signal  Define signal under point as a register at the top of the module.

All key bindings can be seen in a Verilog-buffer with M-x describe-bindings. Key bindings specific to verilog-mode-map are:

\{verilog-mode-map}

Use M-x verilog-delete-auto to remove the AUTOs.

Use M-x verilog-inject-auto to insert AUTOs for the first time.

Use M-x verilog-faq for a pointer to frequently asked questions.

The hooks verilog-before-auto-hook and verilog-auto-hook are called before and after this function, respectively.

For example:

	module ModuleName (/*AUTOARG*/)
	/*AUTOINPUT*/
	/*AUTOOUTPUT*/
	/*AUTOWIRE*/
	/*AUTOREG*/
	InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);

You can also update the AUTOs from the shell using:

	emacs --batch  <filenames.v>  -f verilog-batch-auto

	emacs --batch  <filenames.v>  -f verilog-batch-indent

	emacs --batch  <filenames.v>  -f verilog-batch-delete-auto
	emacs --batch  <filenames.v>  -f verilog-batch-inject-auto

Using M-x describe-function, see also:

    verilog-auto-arg          for AUTOARG module instantiations
    verilog-auto-ascii-enum   for AUTOASCIIENUM enumeration decoding
    verilog-auto-inout-comp  for AUTOINOUTCOMP copy complemented i/o
    verilog-auto-inout-module for AUTOINOUTMODULE copying i/o from elsewhere
    verilog-auto-inout        for AUTOINOUT making hierarchy inouts
    verilog-auto-input        for AUTOINPUT making hierarchy inputs
    verilog-auto-inst         for AUTOINST instantiation pins
    verilog-auto-star         for AUTOINST .* SystemVerilog pins
    verilog-auto-inst-param   for AUTOINSTPARAM instantiation params
    verilog-auto-output       for AUTOOUTPUT making hierarchy outputs
    verilog-auto-output-every for AUTOOUTPUTEVERY making all outputs
    verilog-auto-reg          for AUTOREG registers
    verilog-auto-reg-input    for AUTOREGINPUT instantiation registers
    verilog-auto-reset        for AUTORESET flop resets
    verilog-auto-sense        for AUTOSENSE always sensitivity lists
    verilog-auto-tieoff       for AUTOTIEOFF output tieoffs
    verilog-auto-unused       for AUTOUNUSED unused inputs/inouts
    verilog-auto-wire         for AUTOWIRE instantiation wires

    verilog-read-defines      for reading `define values
    verilog-read-includes     for reading `includes

If you have bugs with these autos, try contacting the AUTOAUTHOR Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.org.

If set, treat signals matching this regexp as active low. This is used for AUTORESET and AUTOTIEOFF. For proper behavior, you will probably also need verilog-auto-reset-widths set.

Concatenation and outputting partial busses is not supported.

Typedefs must match verilog-typedef-regexp, which is disabled by default.

For example:

	module ExampArg (/*AUTOARG*/);
	  input i;
	  output o;
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampArg (/*AUTOARG*/
	  // Outputs
	  o,
	  // Inputs
	  i
	);
	  input i;
	  output o;
	endmodule

Any ports declared between the ( and /*AUTOARG*/ are presumed to be predeclared and are not redeclared by AUTOARG. AUTOARG will make a conservative guess on adding a comma for the first signal, if you have any ifdefs or complicated expressions before the AUTOARG you will need to choose the comma yourself.

Avoid declaring ports manually, as it makes code harder to maintain.

Expand AUTOASCIIENUM statements, as part of M-x verilog-auto. Create a register to contain the ASCII decode of a enumerated signal type. This will allow trace viewers to show the ASCII name of states.

First, parameters are built into a enumeration using the synopsys enum comment. The comment must be between the keyword and the symbol. (Annoying, but that's what Synopsys's dc_shell FSM reader requires.)

Next, registers which that enum applies to are also tagged with the same enum. Synopsys also suggests labeling state vectors, but verilog-mode doesn't care.

Finally, a AUTOASCIIENUM command is used.

The first parameter is the name of the signal to be decoded.

The second parameter is the name to store the ASCII code into. For the signal foo, I suggest the name _foo__ascii, where the leading _ indicates a signal that is just for simulation, and the magic characters _ascii tell viewers like Dinotrace to display in ASCII format.

The final optional parameter is a string which will be removed from the state names.

An example:

	//== State enumeration
	parameter [2:0] // synopsys enum state_info
			   SM_IDLE =  3'b000,
			   SM_SEND =  3'b001,
			   SM_WAIT1 = 3'b010;
	//== State variables
	reg [2:0]	/* synopsys enum state_info */
			state_r;		/* synopsys state_vector state_r */
	reg [2:0]	/* synopsys enum state_info */
			state_e1;

	//== ASCII state decoding

	/*AUTOASCIIENUM("state_r", "state_ascii_r", "SM_")*/

Typing M-x verilog-auto will make this into:

	... same front matter ...

	/*AUTOASCIIENUM("state_r", "state_ascii_r", "SM_")*/
	// Beginning of automatic ASCII enum decoding
	reg [39:0]		state_ascii_r;		// Decode of state_r
	always @(state_r) begin
	   case ({state_r})
		SM_IDLE:  state_ascii_r = "idle ";
		SM_SEND:  state_ascii_r = "send ";
		SM_WAIT1: state_ascii_r = "wait1";
		default:  state_ascii_r = "%Erro";
	   endcase
	end
	// End of automatics

Expand AUTOINOUT statements, as part of M-x verilog-auto. Make inout statements for any inout signal in an /*AUTOINST*/ that isn't declared elsewhere inside the module.

Limitations:

This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls).

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

If any concatenation, or bit-subscripts are missing in the AUTOINSTant's instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).

Typedefs must match verilog-typedef-regexp, which is disabled by default.

Signals matching verilog-auto-inout-ignore-regexp are not included.

An example (see verilog-auto-inst for what else is going on here):

	module ExampInout (ov,i)
	   input i;
	   /*AUTOINOUT*/
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampInout (ov,i)
	   input i;
	   /*AUTOINOUT*/
	   // Beginning of automatic inouts (from unused autoinst inouts)
	   inout [31:0]	ov;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
	     (/*AUTOINST*/
	      // Inouts
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting inouts starting with i:

	   /*AUTOINOUT("^i")*/

Expand AUTOINOUTCOMP statements, as part of M-x verilog-auto. Take input/output/inout statements from the specified module and insert the inverse into the current module (inputs become outputs and vice-versa.) This is useful for making test and stimulus modules which need to have complementing I/O with another module. Any I/O which are already defined in this module will not be redefined.

Limitations:

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

Concatenation and outputting partial busses is not supported.

Module names must be resolvable to filenames. See verilog-auto-inst.

Signals are not inserted in the same order as in the original module, though they will appear to be in the same order to a AUTOINST instantiating either module.

An example:

	module ExampShell (/*AUTOARG*/)
	   /*AUTOINOUTCOMP("ExampMain")*/
	endmodule

	module ExampMain (i,o,io)
          input i;
          output o;
          inout io;
        endmodule

Typing M-x verilog-auto will make this into:

	module ExampShell (/*AUTOARG*/i,o,io)
	   /*AUTOINOUTCOMP("ExampMain")*/
           // Beginning of automatic in/out/inouts (from specific module)
           output i;
           inout io;
           input o;
	   // End of automatics
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting signals starting with i:

	   /*AUTOINOUTCOMP("ExampMain","^i")*/

If set, when creating AUTOINOUT list, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.

Expand AUTOINOUTMODULE statements, as part of M-x verilog-auto. Take input/output/inout statements from the specified module and insert into the current module. This is useful for making null templates and shell modules which need to have identical I/O with another module. Any I/O which are already defined in this module will not be redefined.

Limitations:

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

Concatenation and outputting partial busses is not supported.

Module names must be resolvable to filenames. See verilog-auto-inst.

Signals are not inserted in the same order as in the original module, though they will appear to be in the same order to a AUTOINST instantiating either module.

An example:

	module ExampShell (/*AUTOARG*/)
	   /*AUTOINOUTMODULE("ExampMain")*/
	endmodule

	module ExampMain (i,o,io)
          input i;
          output o;
          inout io;
        endmodule

Typing M-x verilog-auto will make this into:

	module ExampShell (/*AUTOARG*/i,o,io)
	   /*AUTOINOUTMODULE("ExampMain")*/
           // Beginning of automatic in/out/inouts (from specific module)
           output o;
           inout io;
           input i;
	   // End of automatics
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting signals starting with i:

	   /*AUTOINOUTMODULE("ExampMain","^i")*/

Expand AUTOINPUT statements, as part of M-x verilog-auto. Make input statements for any input signal into an /*AUTOINST*/ that isn't declared elsewhere inside the module. This is useful for modules which only instantiate other modules.

Limitations:

This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls).

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

If any concatenation, or bit-subscripts are missing in the AUTOINSTant's instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).

Typedefs must match verilog-typedef-regexp, which is disabled by default.

Signals matching verilog-auto-input-ignore-regexp are not included.

An example (see verilog-auto-inst for what else is going on here):

	module ExampInput (ov,i)
	   output [31:0] ov;
	   /*AUTOINPUT*/
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampInput (ov,i)
	   output [31:0] ov;
	   /*AUTOINPUT*/
	   // Beginning of automatic inputs (from unused autoinst inputs)
	   input	i;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
	     (/*AUTOINST*/
	      // Outputs
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting inputs starting with i:

	   /*AUTOINPUT("^i")*/

If set, when creating AUTOINPUT list, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.

Expand AUTOINST statements, as part of M-x verilog-auto. Replace the pin connections to an instantiation with ones automatically derived from the module header of the instantiated netlist.

If verilog-auto-star-expand is set, also expand SystemVerilog .* ports, and delete them before saving unless verilog-auto-star-save is set. See verilog-auto-star for more information.

Limitations:

Module names must be resolvable to filenames by adding a verilog-library-extensions, and being found in the same directory, or by changing the variable verilog-library-flags or verilog-library-directories. Macros `modname are translated through the vh-{name} Emacs variable, if that is not found, it just ignores the `.

In templates you must have one signal per line, ending in a ), or ));, and have proper () nesting, including a final ); to end the template.

Typedefs must match verilog-typedef-regexp, which is disabled by default.

SystemVerilog multidimensional input/output has only experimental support.

Parameters referenced by the instantiation will remain symbolic, unless verilog-auto-inst-param-value is set.

For example, first take the submodule InstModule.v:

	module InstModule (o,i)
	   output [31:0] o;
	   input i;
	   wire [31:0] o = {32{i}};
	endmodule

This is then used in a upper level module:

	module ExampInst (o,i)
	   output o;
	   input i;
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampInst (o,i)
	   output o;
	   input i;
	   InstModule instName
	     (/*AUTOINST*/
	      // Outputs
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

Where the list of inputs and outputs came from the inst module.

Exceptions:

Unless you are instantiating a module multiple times, or the module is something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY. It just makes for unmaintainable code. To sanitize signal names, try vrename from http://www.veripool.org.

When you need to violate this suggestion there are two ways to list exceptions, placing them before the AUTOINST, or using templates.

Any ports defined before the /*AUTOINST*/ are not included in the list of automatics. This is similar to making a template as described below, but is restricted to simple connections just like you normally make. Also note that any signals before the AUTOINST will only be picked up by AUTOWIRE if you have the appropriate // Input or // Output comment, and exactly the same line formatting as AUTOINST itself uses.

	InstModule instName
          (// Inputs
	   .i		(my_i_dont_mess_with_it),
	   /*AUTOINST*/
	   // Outputs
	   .ov		(ov[31:0]));

Templates:

For multiple instantiations based upon a single template, create a commented out template:

	/* InstModule AUTO_TEMPLATE (
		.sig3	(sigz[]),
		);
	*/

Templates go ABOVE the instantiation(s). When an instantiation is expanded verilog-mode simply searches up for the closest template. Thus you can have multiple templates for the same module, just alternate between the template for an instantiation and the instantiation itself.

The module name must be the same as the name of the module in the instantiation name, and the code "AUTO_TEMPLATE" must be in these exact words and capitalized. Only signals that must be different for each instantiation need to be listed.

Inside a template, a [] in a connection name (with nothing else inside the brackets) will be replaced by the same bus subscript as it is being connected to, or the [] will be removed if it is a single bit signal. Generally it is a good idea to do this for all connections in a template, as then they will work for any width signal, and with AUTOWIRE. See PTL_BUS becoming PTL_BUSNEW below.

If you have a complicated template, set verilog-auto-inst-template-numbers to see which regexps are matching. Don't leave that mode set after debugging is completed though, it will result in lots of extra differences and merge conflicts.

For example:

	/* InstModule AUTO_TEMPLATE (
		.ptl_bus	(ptl_busnew[]),
		);
	*/
	InstModule ms2m (/*AUTOINST*/);

Typing M-x verilog-auto will make this into:

	InstModule ms2m (/*AUTOINST*/
	    // Outputs
	    .NotInTemplate	(NotInTemplate),
	    .ptl_bus		(ptl_busnew[3:0]),  // Templated
	    ....

@ Templates:

It is common to instantiate a cell multiple times, so templates make it trivial to substitute part of the cell name into the connection name.

	/* InstName AUTO_TEMPLATE <optional "REGEXP"> (
		.sig1	(sigx[@]),
		.sig2	(sigy[@"(% (+ 1 @) 4)"]),
		);
	*/

If no regular expression is provided immediately after the AUTO_TEMPLATE keyword, then the @ character in any connection names will be replaced with the instantiation number; the first digits found in the cell's instantiation name.

If a regular expression is provided, the @ character will be replaced with the first () grouping that matches against the cell name. Using a regexp of "\([0-9]+\)" provides identical values for @ as when no regexp is provided. If you use multiple layers of parenthesis, "test\([^0-9]+\)_\([0-9]+\)" would replace @ with non-number characters after test and before _, whereas "\(test\([a-z]+\)_\([0-9]+\)\)" would replace @ with the entire match.

For example:

	/* InstModule AUTO_TEMPLATE (
		.ptl_mapvalidx		(ptl_mapvalid[@]),
		.ptl_mapvalidp1x	(ptl_mapvalid[@"(% (+ 1 @) 4)"]),
		);
	*/
	InstModule ms2m (/*AUTOINST*/);

Typing M-x verilog-auto will make this into:

	InstModule ms2m (/*AUTOINST*/
	    // Outputs
	    .ptl_mapvalidx		(ptl_mapvalid[2]),
	    .ptl_mapvalidp1x		(ptl_mapvalid[3]));

Note the @ character was replaced with the 2 from "ms2m".

Alternatively, using a regular expression for @:

	/* InstModule AUTO_TEMPLATE "_\([a-z]+\)" (
		.ptl_mapvalidx		(@_ptl_mapvalid),
		.ptl_mapvalidp1x	(ptl_mapvalid_@),
		);
	*/
	InstModule ms2_FOO (/*AUTOINST*/);
	InstModule ms2_BAR (/*AUTOINST*/);

Typing M-x verilog-auto will make this into:

	InstModule ms2_FOO (/*AUTOINST*/
	    // Outputs
	    .ptl_mapvalidx		(FOO_ptl_mapvalid),
	    .ptl_mapvalidp1x		(ptl_mapvalid_FOO));
	InstModule ms2_BAR (/*AUTOINST*/
	    // Outputs
	    .ptl_mapvalidx		(BAR_ptl_mapvalid),
	    .ptl_mapvalidp1x		(ptl_mapvalid_BAR));

Regexp Templates:

A template entry of the form

	    .pci_req\([0-9]+\)_l	(pci_req_jtag_[\1]),

will apply an Emacs style regular expression search for any port beginning in pci_req followed by numbers and ending in _l and connecting that to the pci_req_jtag_[] net, with the bus subscript coming from what matches inside the first set of \( \). Thus pci_req2_l becomes pci_req_jtag_[2].

Since \([0-9]+\) is so common and ugly to read, a @ in the port name does the same thing. (Note a @ in the connection/replacement text is completely different -- still use \1 there!) Thus this is the same as the above template:

	    .pci_req@_l		(pci_req_jtag_[\1]),

Here's another example to remove the _l, useful when naming conventions specify _ alone to mean active low. Note the use of [] to keep the bus subscript:

	    .\(.*\)_l		(\1_[]),

Lisp Templates:

First any regular expression template is expanded.

If the syntax @"( ... )" is found in a connection, the expression in quotes will be evaluated as a Lisp expression, with @ replaced by the instantiation number. The MAPVALIDP1X example above would put @+1 modulo 4 into the brackets. Quote all double-quotes inside the expression with a leading backslash (\"). There are special variables defined that are useful in these Lisp functions:

	vl-name        Name portion of the input/output port.
	vl-bits        Bus bits portion of the input/output port ('[2:0]').
	vl-width       Width of the input/output port ('3' for [2:0]).
                       May be a (...) expression if bits isn't a constant.
	vl-dir         Direction of the pin input/output/inout.
	vl-cell-type   Module name/type of the cell ('InstModule').
	vl-cell-name   Instance name of the cell ('instName').

Normal Lisp variables may be used in expressions. See verilog-read-defines which can set vh-{definename} variables for use here. Also, any comments of the form:

	/*AUTO_LISP(setq foo 1)*/

will evaluate any Lisp expression inside the parenthesis between the beginning of the buffer and the point of the AUTOINST. This allows functions to be defined or variables to be changed between instantiations.

Note that when using lisp expressions errors may occur when @ is not a number; you may need to use the standard Emacs Lisp functions `number-to-string' and `string-to-number'.

After the evaluation is completed, @ substitution and [] substitution occur.

Expand AUTOINSTPARAM statements, as part of M-x verilog-auto. Replace the parameter connections to an instantiation with ones automatically derived from the module header of the instantiated netlist.

See M-x verilog-auto-inst for limitations, and templates to customize the output.

For example, first take the submodule InstModule.v:

	module InstModule (o,i)
	   parameter PAR;
	endmodule

This is then used in a upper level module:

	module ExampInst (o,i)
	   parameter PAR;
	   InstModule #(/*AUTOINSTPARAM*/)
		instName (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampInst (o,i)
	   output o;
	   input i;
	   InstModule #(/*AUTOINSTPARAM*/
		        // Parameters
		        .PAR	(PAR));
		instName (/*AUTOINST*/);
	endmodule

Where the list of parameter connections come from the inst module.

Templates:

You can customize the parameter connections using AUTO_TEMPLATEs, just as you would with M-x verilog-auto-inst.

	module InstModule (o,i)
	   parameter WIDTH;
	   input [WIDTH-1:0] i;
	endmodule

	module ExampInst;
	   InstModule

	    instName
	     (/*AUTOINST*/
	      .i 	(i[PARAM-1:0]));

Note even though PARAM=10, the AUTOINST has left the parameter as a symbolic name. If verilog-auto-inst-param-value is set, this will instead expand to:

	module ExampInst;
	   InstModule

	    instName
	     (/*AUTOINST*/
	      .i 	(i[9:0]));

	reg [31:0] a;
	reg b;

	reg [31:0] a;
	reg        b;

	a_long_variable = b + c;
	d = e + f;

	a_long_variable = b + c;
	d               = e + f;

Expand AUTOOUTPUT statements, as part of M-x verilog-auto. Make output statements for any output signal from an /*AUTOINST*/ that isn't a input to another AUTOINST. This is useful for modules which only instantiate other modules.

Limitations:

This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls).

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

If any concatenation, or bit-subscripts are missing in the AUTOINSTant's instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).

Typedefs must match verilog-typedef-regexp, which is disabled by default.

Signals matching verilog-auto-output-ignore-regexp are not included.

An example (see verilog-auto-inst for what else is going on here):

	module ExampOutput (ov,i)
	   input i;
	   /*AUTOOUTPUT*/
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampOutput (ov,i)
	   input i;
	   /*AUTOOUTPUT*/
	   // Beginning of automatic outputs (from unused autoinst outputs)
	   output [31:0]	ov;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
	     (/*AUTOINST*/
	      // Outputs
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting outputs starting with ov:

	   /*AUTOOUTPUT("^ov")*/

Expand AUTOOUTPUTEVERY statements, as part of M-x verilog-auto. Make output statements for any signals that aren't primary inputs or outputs already. This makes every signal in the design a output. This is useful to get Synopsys to preserve every signal in the design, since it won't optimize away the outputs.

An example:

	module ExampOutputEvery (o,i,tempa,tempb)
	   output o;
	   input i;
	   /*AUTOOUTPUTEVERY*/
	   wire tempa = i;
	   wire tempb = tempa;
	   wire o = tempb;
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampOutputEvery (o,i,tempa,tempb)
	   output o;
	   input i;
	   /*AUTOOUTPUTEVERY*/
	   // Beginning of automatic outputs (every signal)
	   output	tempb;
	   output	tempa;
	   // End of automatics
	   wire tempa = i;
	   wire tempb = tempa;
	   wire o = tempb;
	endmodule

If set, when creating AUTOOUTPUT list, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.

Expand AUTOREG statements, as part of M-x verilog-auto. Make reg statements for any output that isn't already declared, and isn't a wire output from a block.

Limitations:

This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls).

This does NOT work on memories, declare those yourself.

An example:

	module ExampReg (o,i)
	   output o;
	   input i;
	   /*AUTOREG*/
	   always o = i;
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampReg (o,i)
	   output o;
	   input i;
	   /*AUTOREG*/
	   // Beginning of automatic regs (for this module's undeclared outputs)
	   reg		o;
	   // End of automatics
	   always o = i;
	endmodule

Expand AUTOREGINPUT statements, as part of M-x verilog-auto. Make reg statements instantiation inputs that aren't already declared. This is useful for making a top level shell for testing the module that is to be instantiated.

Limitations:

This ONLY detects inputs of AUTOINSTants (see verilog-read-sub-decls).

This does NOT work on memories, declare those yourself.

An example (see verilog-auto-inst for what else is going on here):

	module ExampRegInput (o,i)
	   output o;
	   input i;
	   /*AUTOREGINPUT*/
           InstModule instName
             (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampRegInput (o,i)
	   output o;
	   input i;
	   /*AUTOREGINPUT*/
	   // Beginning of automatic reg inputs (for undeclared ...
	   reg [31:0]		iv;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
             (/*AUTOINST*/
	      // Outputs
	      .o		(o[31:0]),
	      // Inputs
	      .iv		(iv));
	endmodule

Expand AUTORESET statements, as part of M-x verilog-auto. Replace the /*AUTORESET*/ comment with code to initialize all registers set elsewhere in the always block.

Limitations:

AUTORESET will not clear memories.

AUTORESET uses <= if there are any <= in the block, else it uses =.

/*AUTORESET*/ presumes that any signals mentioned between the previous begin/case/if statement and the AUTORESET comment are being reset manually and should not be automatically reset. This includes omitting any signals used on the right hand side of assignments.

By default, AUTORESET will include the width of the signal in the autos, this is a recent change. To control this behavior, see verilog-auto-reset-widths.

AUTORESET ties signals to deasserted, which is presumed to be zero. Signals that match verilog-active-low-regexp will be deasserted by tieing them to a one.

An example:

    always @(posedge clk or negedge reset_l) begin
        if (!reset_l) begin
            c <= 1;
            /*AUTORESET*/
        end
        else begin
            a <= in_a;
            b <= in_b;
            c <= in_c;
        end
    end

Typing M-x verilog-auto will make this into:

    always @(posedge core_clk or negedge reset_l) begin
        if (!reset_l) begin
            c <= 1;
            /*AUTORESET*/
            // Beginning of autoreset for uninitialized flops
            a <= 0;
            b <= 0;
            // End of automatics
        end
        else begin
            a <= in_a;
            b <= in_b;
            c <= in_c;
        end
    end

Update automatics with M-x verilog-auto, save the buffer, and compile.

Expand AUTOSENSE statements, as part of M-x verilog-auto. Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short) with one automatically derived from all inputs declared in the always statement. Signals that are generated within the same always block are NOT placed into the sensitivity list (see verilog-auto-sense-include-inputs). Long lines are split based on the `fill-column', see M-x set-fill-column.

Limitations:

Verilog does not allow memories (multidimensional arrays) in sensitivity lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.

Constant signals:

AUTOSENSE cannot always determine if a `define is a constant or a signal (it could be in a include file for example). If a `define or other signal is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT declaration anywhere in the module (parenthesis are required):

	/* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */

Better yet, use a parameter, which will be understood to be constant automatically.

OOps!

If AUTOSENSE makes a mistake, please report it. (First try putting a begin/end after your always!) As a workaround, if a signal that shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above. If a signal should be in the sensitivity list wasn't, placing it before the /*AUTOSENSE*/ comment will prevent it from being deleted when the autos are updated (or added if it occurs there already).

An example:

	   always @ (/*AS*/) begin
	      /* AUTO_CONSTANT (`constant) */
	      outin = ina | inb | `constant;
	      out = outin;
	   end

Typing M-x verilog-auto will make this into:

	   always @ (/*AS*/ina or inb) begin
	      /* AUTO_CONSTANT (`constant) */
	      outin = ina | inb | `constant;
	      out = outin;
	   end

Note in Verilog 2001, you can often get the same result from the new @* operator. (This was added to the language in part due to AUTOSENSE!)

	   always @* begin
	      outin = ina | inb | `constant;
	      out = outin;
	   end

Expand SystemVerilog .* pins, as part of M-x verilog-auto.

If verilog-auto-star-expand is set, .* pins are treated if they were AUTOINST statements, otherwise they are ignored. For safety, Verilog mode will also ignore any .* that are not last in your pin list (this prevents it from deleting pins following the .* when it expands the AUTOINST.)

On writing your file, unless verilog-auto-star-save is set, any non-templated expanded pins will be removed. You may do this at any time with M-x verilog-delete-auto-star-implicit.

If you are converting a module to use .* for the first time, you may wish to use M-x verilog-inject-auto and then replace the created AUTOINST with .*.

See verilog-auto-inst for examples, templates, and more information.

Non-nil indicates to expand a SystemVerilog .* instance ports. They will be expanded in the same way as if there was a AUTOINST in the instantiation. See also verilog-auto-star and verilog-auto-star-save.

Non-nil indicates to save to disk SystemVerilog .* instance expansions. A nil value indicates direct connections will be removed before saving. Only meaningful to those created due to verilog-auto-star-expand being set.

Instead of setting this, you may want to use /*AUTOINST*/, which will always be saved.

Expand AUTOTIEOFF statements, as part of M-x verilog-auto. Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output signals to deasserted.

/*AUTOTIEOFF*/ is used to make stub modules; modules that have the same input/output list as another module, but no internals. Specifically, it finds all outputs in the module, and if that input is not otherwise declared as a register or wire, creates a tieoff.

AUTORESET ties signals to deasserted, which is presumed to be zero. Signals that match verilog-active-low-regexp will be deasserted by tieing them to a one.

An example of making a stub for another module:

    module ExampStub (/*AUTOINST*/);
	/*AUTOINOUTMODULE("Foo")*/
        /*AUTOTIEOFF*/
        // verilator lint_off UNUSED
        wire _unused_ok = &{1'b0,
                            /*AUTOUNUSED*/
                            1'b0};
        // verilator lint_on  UNUSED
    endmodule

Typing M-x verilog-auto will make this into:

    module ExampStub (/*AUTOINST*/...);
	/*AUTOINOUTMODULE("Foo")*/
        // Beginning of autotieoff
        output [2:0] foo;
        // End of automatics

        /*AUTOTIEOFF*/
        // Beginning of autotieoff
        wire [2:0] foo = 3'b0;
        // End of automatics
        ...
    endmodule

Expand AUTOUNUSED statements, as part of M-x verilog-auto. Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused input and inout signals.

/*AUTOUNUSED*/ is used to make stub modules; modules that have the same input/output list as another module, but no internals. Specifically, it finds all inputs and inouts in the module, and if that input is not otherwise used, adds it to a comma separated list.

The comma separated list is intended to be used to create a _unused_ok signal. Using the exact name "_unused_ok" for name of the temporary signal is recommended as it will insure maximum forward compatibility, it also makes lint warnings easy to understand; ignore any unused warnings with "unused" in the signal name.

To reduce simulation time, the _unused_ok signal should be forced to a constant to prevent wiggling. The easiest thing to do is use a reduction-and with 1'b0 as shown.

This way all unused signals are in one place, making it convenient to add your tool's specific pragmas around the assignment to disable any unused warnings.

You can add signals you do not want included in AUTOUNUSED with verilog-auto-unused-ignore-regexp.

An example of making a stub for another module:

    module ExampStub (/*AUTOINST*/);
	/*AUTOINOUTMODULE("Examp")*/
        /*AUTOTIEOFF*/
        // verilator lint_off UNUSED
        wire _unused_ok = &{1'b0,
                            /*AUTOUNUSED*/
                            1'b0};
        // verilator lint_on  UNUSED
    endmodule

Typing M-x verilog-auto will make this into:

        ...
        // verilator lint_off UNUSED
        wire _unused_ok = &{1'b0,
                            /*AUTOUNUSED*/
			    // Beginning of automatics
			    unused_input_a,
			    unused_input_b,
			    unused_input_c,
			    // End of automatics
                            1'b0};
        // verilator lint_on  UNUSED
    endmodule

If set, when creating AUTOUNUSED list, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.

Expand AUTOWIRE statements, as part of M-x verilog-auto. Make wire statements for instantiations outputs that aren't already declared.

Limitations:

This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls), and all busses must have widths, such as those from AUTOINST, or using [] in AUTO_TEMPLATEs.

This does NOT work on memories or SystemVerilog .name connections, declare those yourself.

Verilog mode will add "Couldn't Merge" comments to signals it cannot determine how to bus together. This occurs when you have ports with non-numeric or non-sequential bus subscripts. If Verilog mode mis-guessed, you'll have to declare them yourself.

An example (see verilog-auto-inst for what else is going on here):

	module ExampWire (o,i)
	   output o;
	   input i;
	   /*AUTOWIRE*/
           InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampWire (o,i)
	   output o;
	   input i;
	   /*AUTOWIRE*/
	   // Beginning of automatic wires
	   wire [31:0]		ov;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
	     (/*AUTOINST*/
	      // Outputs
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	   wire o = | ov;
	endmodule

Put the region into a Verilog comment. The comments that are in this area are "deformed": `*)' becomes `!(*' and `}' becomes `!{'. These deformed comments are returned to normal if you use M-x verilog-uncomment-region to undo the commenting.

The commented area starts with verilog-exclude-str-start, and ends with verilog-exclude-str-end. But if you change these variables, M-x verilog-uncomment-region won't recognize the comments.

Program and arguments to use to compile Verilog source. Depending on the verilog-set-compile-command, this may be invoked when you type M-x compile. When the compile completes, M-x next-error will take you to the next lint error.

Complete word at current point. (See also verilog-toggle-completions, verilog-type-keywords, and verilog-separator-keywords.)

Program and arguments to use to annotate for coverage Verilog source. Depending on the verilog-set-compile-command, this may be invoked when you type M-x compile. When the compile completes, M-x next-error will take you to the next lint error.

Delete the automatic outputs, regs, and wires created by M-x verilog-auto. Use M-x verilog-auto to re-insert the updated AUTOs.

The hooks verilog-before-delete-auto-hook and verilog-delete-auto-hook are called before and after this function, respectively.

Delete all .* implicit connections created by verilog-auto-star. This function will be called automatically at save unless verilog-auto-star-save is set, any non-templated expanded pins will be removed.

	module ExampInject (i, o);
	  input i;
	  input j;
	  output o;
	  always @ (i or j)
	     o = i | j;
	  InstModule instName
            (.foobar(baz),
	     j(j));
	endmodule

Typing M-x verilog-inject-auto will make this into:

	module ExampInject (i, o/*AUTOARG*/
	  // Inputs
	  j);
	  input i;
	  output o;
	  always @ (/*AS*/i or j)
	     o = i | j;
	  InstModule instName
            (.foobar(baz),
	     /*AUTOINST*/
	     // Outputs
	     j(j));
	endmodule

    // Local Variables:
    // verilog-library-directories:("." "subdir" "subdir2")
    // End:

See also verilog-library-flags, verilog-library-files and verilog-library-extensions.

List of extensions to use when looking for files for /*AUTOINST*/. See also verilog-library-flags, verilog-library-directories.

    // Local Variables:
    // verilog-library-files:("/some/path/technology.v" "/some/path/tech2.v")
    // End:

See also verilog-library-flags, verilog-library-directories.

List of standard Verilog arguments to use for /*AUTOINST*/. These arguments are used to find files for verilog-auto, and match the flags accepted by a standard Verilog-XL simulator.

    -f filename     Reads more verilog-library-flags from the filename.
    +incdir+dir     Adds the directory to verilog-library-directories.
    -Idir           Adds the directory to verilog-library-directories.
    -y dir          Adds the directory to verilog-library-directories.
    +libext+.v      Adds the extensions to verilog-library-extensions.
    -v filename     Adds the filename to verilog-library-files.

    filename        Adds the filename to verilog-library-files.
                    This is not recommended, -v is a better choice.

You might want these defined in each file; put at the *END* of your file something like:

    // Local Variables:
    // verilog-library-flags:("-y dir -y otherdir")
    // End:

Verilog-mode attempts to detect changes to this local variable, but they are only insured to be correct when the file is first visited. Thus if you have problems, use M-x find-alternate-file RET to have these take effect.

See also the variables mentioned above.

Unix program and arguments to call to run a lint checker on Verilog source. Depending on the verilog-set-compile-command, this may be invoked when you type M-x compile. When the compile completes, M-x next-error will take you to the next lint error.

Read `defines and parameters for the current file, or optional FILENAME. If the filename is provided, verilog-library-flags will be used to resolve it. If optional RECURSE is non-nil, recurse through `includes.

Parameters must be simple assignments to constants, or have their own "parameter" label rather than a list of parameters. Thus:

    parameter X = 5, Y = 10;	// Ok
    parameter X = {1'b1, 2'h2};	// Ok
    parameter X = {1'b1, 2'h2}, Y = 10;	// Bad, make into 2 parameter lines

Defines must be simple text substitutions, one on a line, starting at the beginning of the line. Any ifdefs or multiline comments around the define are ignored.

Defines are stored inside Emacs variables using the name vh-{definename}.

This function is useful for setting vh-* variables. The file variables feature can be used to set defines that verilog-mode can see; put at the *END* of your file something like:

    // Local Variables:
    // vh-macro:"macro_definition"
    // End:

If macros are defined earlier in the same file and you want their values, you can read them automatically (provided `enable-local-eval' is on):

    // Local Variables:
    // eval:(verilog-read-defines)
    // eval:(verilog-read-defines "group_standard_includes.v")
    // End:

Note these are only read when the file is first visited, you must use M-x find-alternate-file RET to have these take effect after editing them!

If you want to disable the "Process `eval' or hook local variables" warning message, you need to add to your .emacs file:

    (setq enable-local-eval t)

Read `includes for the current file. This will find all of the `includes which are at the beginning of lines, ignoring any ifdefs or multiline comments around them. verilog-read-defines is then performed on the current and each included file.

It is often useful put at the *END* of your file something like:

    // Local Variables:
    // eval:(verilog-read-defines)
    // eval:(verilog-read-includes)
    // End:

Note includes are only read when the file is first visited, you must use M-x find-alternate-file RET to have these take effect after editing them!

It is good to get in the habit of including all needed files in each .v file that needs it, rather than waiting for compile time. This will aid this process, Verilint, and readability. To prevent defining the same variable over and over when many modules are compiled together, put a test around the inside each include file:

foo.v (a include):

	`ifdef _FOO_V	// include if not already included
	`else
	`define _FOO_V
	... contents of file
	`endif // _FOO_V

This only works on instantiations created with /*AUTOINST*/ converted by M-x verilog-auto-inst. Otherwise, it would have to read in the whole component library to determine connectivity of the design.

One work around for this problem is to manually create // Inputs and // Outputs comments above subcell signals, for example:

	module ModuleName (
	    // Outputs
	    .out (out),
	    // Inputs
	    .in  (in));

This reads verilog-tool and sets `compile-command'. This specifies the program that executes when you type M-x compile or M-x verilog-auto-save-compile.

By default verilog-tool uses a Makefile if one exists in the current directory. If not, it is set to the verilog-linter, verilog-coverage, verilog-simulator, or verilog-compiler variables, as selected with the Verilog -> "Choose Compilation Action" menu.

You should set verilog-tool or the other variables to the path and arguments for your Verilog simulator. For example:

    "vcs -p123 -O"

    "(cd /tmp; surecov %s)".

In the former case, the path to the current buffer is concat'ed to the value of verilog-tool; in the later, the path to the current buffer is substituted for the %s.

Where __FILE__ appears in the string, the `buffer-file-name' of the current buffer, without the directory portion, will be substituted.

Program and arguments to use to interpret Verilog source. Depending on the verilog-set-compile-command, this may be invoked when you type M-x compile. When the compile completes, M-x next-error will take you to the next lint error.

True means M-x verilog-complete-word should try all possible completions one by one. Repeated use of M-x verilog-complete-word will show you all of them. Normally, when there is more than one possible completion, it displays a list of all possible completions.

Which tool to use for building compiler-command. Either nil, `verilog-linter, `verilog-coverage, `verilog-simulator, or `verilog-compiler. Alternatively use the "Choose Compilation Action" menu. See verilog-set-compile-command for more information.

Uncomment a commented area; change deformed comments back to normal. This command does nothing if the pointer is not in a commented area. See also verilog-comment-region.