Verilog-Perl

Verilog::Language 3.040 2008/08/20

• Add Netlist::Net->value containing parameter values. [Ron D Smith]

• Added Verilog::Netlist/Verilog::Parser preproc option. [by Miguel Corazao, AMD]

• Support =, -=, etc, and +, -- operators. [Sean de la Haye]

• Support "cover property."

• Eliminated automatic error printing upon application termination. [by Miguel Corazao, AMD]

• Fix syntax error when "`include `defname" is ifdefed. [John Dickol]

• Fix error when macro call has commas in concatenate. [John Dickol]

• Fix compile errors under Fedora 9, GCC 4.3.0. [by Jeremy Bennett]

Verilog::Language 3.025 2008/05/07

• Fix "output reg name=expr;" bug34649 syntax error. [Martin Scharrer]

• Fix functions with "input integer". [Johan Wouters]

• Fix bug introduced in 3.024 with parametrized defines.

• Fix compiler warnings under GCC 4.2.1.

• Fix "endclass" keyword misspelling. [John Dickol]

• Fix preprocessor `else after series of `elsif. [Mark Nodine]

• Fix parametrized defines calling define with comma. [Joshua Wise]

Verilog::Language 3.024 2008/04/02 is released:

• Verilog::Parser will now start parsing using the keywords based on the Verilog::Language::language_standard setting.

• Fix vhier ignoring --language option. [Martin Scharrer]

• Fix SystemVerilog parameterized defines with `` expansion, and fix extra whitespace inserted on substitution. [Vladimir Matveyenko]

• Fix missing uwire keyword in Verilog::Language. [Jonathan David]

• Fix parse error on min:typ:max delay pairs, bug34575. [Martin Scharrer]