Verilog-Perl

This code is not parsed correctly...
module assertion_error;
    wire clk;
    wire rst_n;
    reg a;
    reg b;    
    sample_assertion: assert property (
        @(posedge clk)
            disable iff (!rst_n)
                (a !== b)
    );
endmodule

I receive this error:
%Error: assertion_error.sv:6: syntax error, unexpected ':', expecting '('
Exiting due to errors

I'm using version 3.035 of Verilog-Perl on a RedHat Opteron machine.