Verilog-Perl

This may be an enhancment vs. a bug.

I'm using vhier to find all the files used in my design + testbench. It doesn't like the SV interfaces I'm using. Specifically, the following items within an interface cause errors:

- port list - signal (wire, etc.) definitions - clocking blocks - always blocks

Here's a sample file to illustrate the problem. The error messages I get are embedded as comments in the file. I used ifdefs to exclude the unsupported code and proceed to the next error.

interface ifc(

// %Error: vhier_ifc.sv:6: Signal declaration outside of module definition
// Can't call method "_portsordered" on an undefined value at /usr/local/share/perl5/site_perl/5.8.5/i686-linux/Verilog/Netlist/File.pm line 113.
`ifndef NO_PORTS
        input bit clk
`endif
);

  wire [31:0] addr;
  wire [31:0] data;
  int count = 0;

// %Error: vhier_ifc.sv:16: syntax error, unexpected "clocking" 
`ifndef NO_CLOCKING
  clocking mck @(posedge clk);
    default input #1 output #1;
    output addr, data;
  endclocking

  clocking pck @(posedge clk);
    default input #1 output #1;
    input addr, data;
  endclocking
`endif

// %Error: vhier_ifc.sv:29: syntax error, unexpected "always" 
`ifndef NO_ALWAYS
  always @(posedge clk) count = count+1;
`endif

  modport master  (clocking mck);
  modport passive (clocking pck);

endinterface

module top;
  bit clk = 0;

// %Error: vhier_ifc.sv:41: Cannot find ifc
  ifc ifc_1(clk);
endmodule