Verilator

Hello,

I have a problem simulating this structure:

wire [dataWidth_bcm-1:0] inMask [0:numberOfInputs-1];
wire [dataWidth_bcm-1:0] inMaskLink [0:numberOfInputs-1];
wire [numberOfInputs_log-1:0] seqSelectedIn_out_mask [0:numberOfInputs-1];
wire [numberOfInputs_log-1:0] seqSelectedIn_out_maskLink [0:numberOfInputs-1];

generate for( i = 0; i < numberOfInputs; i = i + 1 ) begin: inputMask
        assign inMask[i] = {seqPriority_in[(i+1)*priorityWidth-1:i*priorityWidth],
                            seqData_in[(i+1)*dataWidth-1:i*dataWidth]} &
                                {(dataWidth_bcm){dataSelect[i]}};
        assign seqSelectedIn_out_mask[i] = dataSelect[i] ? i : 0; 
end
endgenerate

assign inMaskLink[0] = inMask[0];
assign seqSelectedIn_out_maskLink[0] = seqSelectedIn_out_mask[0];
generate for( i = 1; i < numberOfInputs; i = i + 1 ) begin: inputMaskInterLink
        assign  inMaskLink[i] = inMask[i]|inMaskLink[i-1];
        assign  seqSelectedIn_out_maskLink[i] = seqSelectedIn_out_mask[i]|seqSelectedIn_out_maskLink[i-1];
end
endgenerate

Firstly, it throws an UNOPTFLAT warning for signal inMaskLink:

%Warning-UNOPTFLAT: Arbiter_v3.v:184: Signal unoptimizable: Feedback to clock or circular logic: TOP->v.ubc_top.inStorageInterface.arbiter4_v3.gen_arbiter.inMaskLink
%Warning-UNOPTFLAT:      Example path: Arbiter_v3.v:184:  TOP->v.ubc_top.inStorageInterface.arbiter4_v3.gen_arbiter.inMaskLink
%Warning-UNOPTFLAT:      Example path: Arbiter_v3.v:199:  ASSIGNW
%Warning-UNOPTFLAT:      Example path: Arbiter_v3.v:184:  TOP->v.ubc_top.inStorageInterface.arbiter4_v3.gen_arbiter.inMaskLink

Then, it throws an error:

%Error: Arbiter_v3.v:184: Unsupported: Can't detect changes on arrayed variable (probably with UNOPTFLAT warning suppressed): v.ubc_top.inStorageInterface.arbiter4_v3.gen_arbiter.inMaskLink

Verilator probably believes that the second generate is a circular CLC assignment but actually it's not. Any suggestions please?