Verilog-Perl - vrename changes the signals with same name in different modules

vrename changes the signals with same name in different modules

Added by Hanken Hwang 136 days ago

Say I got 2 different verilog modules (A and B) in RTL, each module has a wire signal with same name data_001; Now I want to use vrename to change data_001 in module A to data_002 without touching this signal in module B (some other signals in module B might need to rename meanwhile). Then vrename will make trouble. It lists all the sorted signals in signals.vrename and it always changes all the signals with the same name at the same time. While in real world implementation, we often need to rename some signals in specified scope of modules.

It is certainly not vrename's bug, but I could suggest to add a signal scope concept into vrename to enhance the robustness of functionality. Simply say, we need the signals.vrename like: @# Generated by vrename on Fri Jul 18 12:52:37 2008 #

Files read for this analysis: vfile "moulde_A.v"
Original Signal Name Name to change to
-------------------- ----------------- # sigren "data_001" "data_001" .......(other signals)

vfile "moulde_B.v"

Original Signal Name Name to change to
-------------------- ----------------- # sigren "data_001" "data_001" .......(other signals)@

So if we want rename signal in module A, we only need to change the signal within A section.

One thing should be notified: if the the signal need to be renamed is the port of module A. While module B calls module A as a instance, then in Module B the instance name should be changed accordingly. I think this would be easily done in perl script.

Replies

RE: vrename changes the signals with same name in different modules - Added by Wilson Snyder 136 days ago

You probably realize this, but you can run the --change on only one of the files.

I can see how that's useful. I can add what you suggest, but can't do the detect-a-port and still change it, because there isn't enough knowledge in vrename to implement this (it gets very hairy to know what the subcells are without resolving defines and such.) Is that still worthwhile?

RE: vrename changes the signals with same name in different modules - Added by Hanken Hwang 134 days ago

Hey, Wilson, thanks for your answer! You know real pain is the signals need to be renamed belong to overlapped subset. For instance, besides what I mentioned, I still got a wire signal called "data_003" in two files which needs to be changed to "data_004" for both. Then I cannot automatically do the renaming in ONE step.

I don't know how difficult to make it work for detect-and-change-port. At least I think you can devide the signals in signals.vrename into 2 parts, one is pure signals which are reg, wire, or any else internal signals, the other is port signals. Pure signals can be renamed for specified modules, while port signal should be changed for all modules. That would be a possible way for vrename.

I don't know if your verilog parser can deal with detecting module instance in RTL. If so, it's not so difficult to do detect-and-change-port for vrename, you know, it just adds some conditional decision to make vrename smarter. If not, you might try RVP//www.burbleland.com/v2html/rvp.html">http://www.burbleland.com/v2html/rvp.html

Anyway, it's easy to say than done. Please pardon me if I underestimate the workload you might spend on vrename. I know a little bit Perl programming and I am willing to help. Let me know when you need someone who can help to test, verify, or write a simple perl script. :)